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https://github.com/ZDoom/raze-gles.git
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718112a8fe
Currently none of these is being used, but eventually they will, once more code gets ported over. So it's better to have them right away and avoid editing the project file too much, only to revert that later.
380 lines
9.3 KiB
C++
380 lines
9.3 KiB
C++
// SPC emulation support: init, sample buffering, reset, SPC loading
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// Game_Music_Emu https://bitbucket.org/mpyne/game-music-emu/
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#include "Snes_Spc.h"
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#include <string.h>
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/* Copyright (C) 2004-2007 Shay Green. This module is free software; you
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can redistribute it and/or modify it under the terms of the GNU Lesser
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General Public License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version. This
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module is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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details. You should have received a copy of the GNU Lesser General Public
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License along with this module; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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#include "blargg_source.h"
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#define RAM (m.ram.ram)
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#define REGS (m.smp_regs [0])
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#define REGS_IN (m.smp_regs [1])
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// (n ? n : 256)
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#define IF_0_THEN_256( n ) ((uint8_t) ((n) - 1) + 1)
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//// Init
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blargg_err_t Snes_Spc::init()
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{
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memset( &m, 0, sizeof m );
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dsp.init( RAM );
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m.tempo = tempo_unit;
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// Most SPC music doesn't need ROM, and almost all the rest only rely
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// on these two bytes
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m.rom [0x3E] = 0xFF;
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m.rom [0x3F] = 0xC0;
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static unsigned char const cycle_table [128] =
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{// 01 23 45 67 89 AB CD EF
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0x28,0x47,0x34,0x36,0x26,0x54,0x54,0x68, // 0
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0x48,0x47,0x45,0x56,0x55,0x65,0x22,0x46, // 1
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0x28,0x47,0x34,0x36,0x26,0x54,0x54,0x74, // 2
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0x48,0x47,0x45,0x56,0x55,0x65,0x22,0x38, // 3
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0x28,0x47,0x34,0x36,0x26,0x44,0x54,0x66, // 4
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0x48,0x47,0x45,0x56,0x55,0x45,0x22,0x43, // 5
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0x28,0x47,0x34,0x36,0x26,0x44,0x54,0x75, // 6
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0x48,0x47,0x45,0x56,0x55,0x55,0x22,0x36, // 7
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0x28,0x47,0x34,0x36,0x26,0x54,0x52,0x45, // 8
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0x48,0x47,0x45,0x56,0x55,0x55,0x22,0xC5, // 9
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0x38,0x47,0x34,0x36,0x26,0x44,0x52,0x44, // A
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0x48,0x47,0x45,0x56,0x55,0x55,0x22,0x34, // B
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0x38,0x47,0x45,0x47,0x25,0x64,0x52,0x49, // C
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0x48,0x47,0x56,0x67,0x45,0x55,0x22,0x83, // D
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0x28,0x47,0x34,0x36,0x24,0x53,0x43,0x40, // E
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0x48,0x47,0x45,0x56,0x34,0x54,0x22,0x60, // F
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};
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// unpack cycle table
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for ( int i = 0; i < 128; i++ )
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{
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int n = cycle_table [i];
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m.cycle_table [i * 2 + 0] = n >> 4;
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m.cycle_table [i * 2 + 1] = n & 0x0F;
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}
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#if SPC_LESS_ACCURATE
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memcpy( reg_times, reg_times_, sizeof reg_times );
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#endif
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reset();
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return 0;
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}
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void Snes_Spc::init_rom( uint8_t const in [rom_size] )
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{
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memcpy( m.rom, in, sizeof m.rom );
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}
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void Snes_Spc::set_tempo( int t )
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{
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m.tempo = t;
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int const timer2_shift = 4; // 64 kHz
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int const other_shift = 3; // 8 kHz
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#if SPC_DISABLE_TEMPO
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m.timers [2].prescaler = timer2_shift;
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m.timers [1].prescaler = timer2_shift + other_shift;
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m.timers [0].prescaler = timer2_shift + other_shift;
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#else
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if ( !t )
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t = 1;
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int const timer2_rate = 1 << timer2_shift;
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int rate = (timer2_rate * tempo_unit + (t >> 1)) / t;
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if ( rate < timer2_rate / 4 )
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rate = timer2_rate / 4; // max 4x tempo
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m.timers [2].prescaler = rate;
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m.timers [1].prescaler = rate << other_shift;
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m.timers [0].prescaler = rate << other_shift;
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#endif
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}
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// Timer registers have been loaded. Applies these to the timers. Does not
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// reset timer prescalers or dividers.
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void Snes_Spc::timers_loaded()
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{
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int i;
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for ( i = 0; i < timer_count; i++ )
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{
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Timer* t = &m.timers [i];
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t->period = IF_0_THEN_256( REGS [r_t0target + i] );
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t->enabled = REGS [r_control] >> i & 1;
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t->counter = REGS_IN [r_t0out + i] & 0x0F;
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}
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set_tempo( m.tempo );
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}
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// Loads registers from unified 16-byte format
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void Snes_Spc::load_regs( uint8_t const in [reg_count] )
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{
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memcpy( REGS, in, reg_count );
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memcpy( REGS_IN, REGS, reg_count );
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// These always read back as 0
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REGS_IN [r_test ] = 0;
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REGS_IN [r_control ] = 0;
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REGS_IN [r_t0target] = 0;
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REGS_IN [r_t1target] = 0;
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REGS_IN [r_t2target] = 0;
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}
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// RAM was just loaded from SPC, with $F0-$FF containing SMP registers
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// and timer counts. Copies these to proper registers.
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void Snes_Spc::ram_loaded()
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{
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m.rom_enabled = 0;
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load_regs( &RAM [0xF0] );
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// Put STOP instruction around memory to catch PC underflow/overflow
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memset( m.ram.padding1, cpu_pad_fill, sizeof m.ram.padding1 );
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memset( m.ram.ram + 0x10000, cpu_pad_fill, sizeof m.ram.padding1 );
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}
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// Registers were just loaded. Applies these new values.
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void Snes_Spc::regs_loaded()
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{
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enable_rom( REGS [r_control] & 0x80 );
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timers_loaded();
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}
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void Snes_Spc::reset_time_regs()
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{
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m.cpu_error = 0;
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m.echo_accessed = 0;
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m.spc_time = 0;
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m.dsp_time = 0;
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#if SPC_LESS_ACCURATE
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m.dsp_time = clocks_per_sample + 1;
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#endif
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for ( int i = 0; i < timer_count; i++ )
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{
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Timer* t = &m.timers [i];
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t->next_time = 1;
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t->divider = 0;
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}
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regs_loaded();
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m.extra_clocks = 0;
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reset_buf();
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}
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void Snes_Spc::reset_common( int timer_counter_init )
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{
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int i;
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for ( i = 0; i < timer_count; i++ )
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REGS_IN [r_t0out + i] = timer_counter_init;
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// Run IPL ROM
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memset( &m.cpu_regs, 0, sizeof m.cpu_regs );
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m.cpu_regs.pc = rom_addr;
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REGS [r_test ] = 0x0A;
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REGS [r_control] = 0xB0; // ROM enabled, clear ports
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for ( i = 0; i < port_count; i++ )
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REGS_IN [r_cpuio0 + i] = 0;
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reset_time_regs();
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}
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void Snes_Spc::soft_reset()
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{
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reset_common( 0 );
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dsp.soft_reset();
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}
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void Snes_Spc::reset()
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{
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memset( RAM, 0xFF, 0x10000 );
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ram_loaded();
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reset_common( 0x0F );
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dsp.reset();
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}
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char const Snes_Spc::signature [signature_size + 1] =
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"SNES-SPC700 Sound File Data v0.30\x1A\x1A";
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blargg_err_t Snes_Spc::load_spc( void const* data, long size )
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{
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spc_file_t const* const spc = (spc_file_t const*) data;
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// be sure compiler didn't insert any padding into fle_t
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assert( sizeof (spc_file_t) == spc_min_file_size + 0x80 );
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// Check signature and file size
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if ( size < signature_size || memcmp( spc, signature, 27 ) )
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return "Not an SPC file";
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if ( size < spc_min_file_size )
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return "Corrupt SPC file";
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// CPU registers
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m.cpu_regs.pc = spc->pch * 0x100 + spc->pcl;
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m.cpu_regs.a = spc->a;
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m.cpu_regs.x = spc->x;
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m.cpu_regs.y = spc->y;
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m.cpu_regs.psw = spc->psw;
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m.cpu_regs.sp = spc->sp;
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// RAM and registers
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memcpy( RAM, spc->ram, 0x10000 );
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ram_loaded();
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// DSP registers
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dsp.load( spc->dsp );
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reset_time_regs();
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return 0;
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}
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void Snes_Spc::clear_echo()
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{
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if ( !(dsp.read( Spc_Dsp::r_flg ) & 0x20) )
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{
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int addr = 0x100 * dsp.read( Spc_Dsp::r_esa );
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int end = addr + 0x800 * (dsp.read( Spc_Dsp::r_edl ) & 0x0F);
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if ( end > 0x10000 )
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end = 0x10000;
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memset( &RAM [addr], 0xFF, end - addr );
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}
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}
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//// Sample output
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void Snes_Spc::reset_buf()
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{
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// Start with half extra buffer of silence
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sample_t* out = m.extra_buf;
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while ( out < &m.extra_buf [extra_size / 2] )
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*out++ = 0;
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m.extra_pos = out;
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m.buf_begin = 0;
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dsp.set_output( 0, 0 );
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}
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void Snes_Spc::set_output( sample_t* out, int size )
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{
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require( (size & 1) == 0 ); // size must be even
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m.extra_clocks &= clocks_per_sample - 1;
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if ( out )
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{
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sample_t const* out_end = out + size;
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m.buf_begin = out;
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m.buf_end = out_end;
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// Copy extra to output
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sample_t const* in = m.extra_buf;
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while ( in < m.extra_pos && out < out_end )
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*out++ = *in++;
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// Handle output being full already
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if ( out >= out_end )
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{
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// Have DSP write to remaining extra space
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out = dsp.extra();
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out_end = &dsp.extra() [extra_size];
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// Copy any remaining extra samples as if DSP wrote them
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while ( in < m.extra_pos )
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*out++ = *in++;
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assert( out <= out_end );
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}
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dsp.set_output( out, out_end - out );
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}
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else
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{
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reset_buf();
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}
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}
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void Snes_Spc::save_extra()
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{
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// Get end pointers
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sample_t const* main_end = m.buf_end; // end of data written to buf
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sample_t const* dsp_end = dsp.out_pos(); // end of data written to dsp.extra()
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if ( m.buf_begin <= dsp_end && dsp_end <= main_end )
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{
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main_end = dsp_end;
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dsp_end = dsp.extra(); // nothing in DSP's extra
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}
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// Copy any extra samples at these ends into extra_buf
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sample_t* out = m.extra_buf;
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sample_t const* in;
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for ( in = m.buf_begin + sample_count(); in < main_end; in++ )
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*out++ = *in;
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for ( in = dsp.extra(); in < dsp_end ; in++ )
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*out++ = *in;
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m.extra_pos = out;
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assert( out <= &m.extra_buf [extra_size] );
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}
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blargg_err_t Snes_Spc::play( int count, sample_t* out )
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{
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require( (count & 1) == 0 ); // must be even
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if ( count )
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{
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set_output( out, count );
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end_frame( count * (clocks_per_sample / 2) );
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}
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const char* err = m.cpu_error;
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m.cpu_error = 0;
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return err;
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}
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blargg_err_t Snes_Spc::skip( int count )
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{
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#if SPC_LESS_ACCURATE
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if ( count > 2 * sample_rate * 2 )
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{
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set_output( 0, 0 );
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// Skip a multiple of 4 samples
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time_t end = count;
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count = (count & 3) + 1 * sample_rate * 2;
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end = (end - count) * (clocks_per_sample / 2);
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m.skipped_kon = 0;
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m.skipped_koff = 0;
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// Preserve DSP and timer synchronization
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// TODO: verify that this really preserves it
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int old_dsp_time = m.dsp_time + m.spc_time;
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m.dsp_time = end - m.spc_time + skipping_time;
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end_frame( end );
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m.dsp_time = m.dsp_time - skipping_time + old_dsp_time;
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dsp.write( Spc_Dsp::r_koff, m.skipped_koff & ~m.skipped_kon );
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dsp.write( Spc_Dsp::r_kon , m.skipped_kon );
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clear_echo();
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}
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#endif
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return play( count, 0 );
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}
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