mirror of
https://github.com/ZDoom/raze-gles.git
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718112a8fe
Currently none of these is being used, but eventually they will, once more code gets ported over. So it's better to have them right away and avoid editing the project file too much, only to revert that later.
1182 lines
22 KiB
C
1182 lines
22 KiB
C
// Game_Music_Emu https://bitbucket.org/mpyne/game-music-emu/
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/* Copyright (C) 2004-2007 Shay Green. This module is free software; you
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can redistribute it and/or modify it under the terms of the GNU Lesser
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General Public License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version. This
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module is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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details. You should have received a copy of the GNU Lesser General Public
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License along with this module; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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//// Memory access
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#if SPC_MORE_ACCURACY
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#define SUSPICIOUS_OPCODE( name ) ((void) 0)
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#else
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#define SUSPICIOUS_OPCODE( name ) debug_printf( "SPC: suspicious opcode: " name "\n" )
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#endif
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#define CPU_READ( time, offset, addr )\
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cpu_read( addr, time + offset )
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#define CPU_WRITE( time, offset, addr, data )\
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cpu_write( data, addr, time + offset )
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#if SPC_MORE_ACCURACY
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#define CPU_READ_TIMER( time, offset, addr, out )\
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{ out = CPU_READ( time, offset, addr ); }
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#else
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// timers are by far the most common thing read from dp
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#define CPU_READ_TIMER( time, offset, addr_, out )\
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{\
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rel_time_t adj_time = time + offset;\
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int dp_addr = addr_;\
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int ti = dp_addr - (r_t0out + 0xF0);\
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if ( (unsigned) ti < timer_count )\
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{\
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Timer* t = &m.timers [ti];\
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if ( adj_time >= t->next_time )\
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t = run_timer_( t, adj_time );\
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out = t->counter;\
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t->counter = 0;\
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}\
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else\
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{\
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out = ram [dp_addr];\
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int i = dp_addr - 0xF0;\
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if ( (unsigned) i < 0x10 )\
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out = cpu_read_smp_reg( i, adj_time );\
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}\
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}
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#endif
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#define TIME_ADJ( n ) (n)
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#define READ_TIMER( time, addr, out ) CPU_READ_TIMER( rel_time, TIME_ADJ(time), (addr), out )
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#define READ( time, addr ) CPU_READ ( rel_time, TIME_ADJ(time), (addr) )
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#define WRITE( time, addr, data ) CPU_WRITE( rel_time, TIME_ADJ(time), (addr), (data) )
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#define DP_ADDR( addr ) (dp + (addr))
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#define READ_DP_TIMER( time, addr, out ) CPU_READ_TIMER( rel_time, TIME_ADJ(time), DP_ADDR( addr ), out )
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#define READ_DP( time, addr ) READ ( time, DP_ADDR( addr ) )
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#define WRITE_DP( time, addr, data ) WRITE( time, DP_ADDR( addr ), data )
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#define READ_PROG16( addr ) (RAM [(addr) & 0xffff] | (RAM [((addr) + 1) & 0xffff] << 8))
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#define SET_PC( n ) (pc = n)
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#define GET_PC() (pc)
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#define READ_PC( pc ) (ram [pc])
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#define READ_PC16( pc ) READ_PROG16( pc )
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#define SET_SP( v ) (sp = v)
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#define GET_SP() ((uint8_t) (sp))
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#define PUSH16( data )\
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{\
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PUSH( (data & 0xff00) >> 8 );\
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PUSH( data & 0xff );\
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}
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#define PUSH( data )\
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{\
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ram [0x100 + sp] = (uint8_t) (data);\
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--sp;\
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}
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#define POP( out )\
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{\
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++sp;\
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out = ram [0x100 + sp];\
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}
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#define MEM_BIT( rel ) CPU_mem_bit( pc, rel_time + rel )
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unsigned Snes_Spc::CPU_mem_bit( uint16_t pc, rel_time_t rel_time )
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{
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unsigned addr = READ_PC16( pc );
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unsigned t = READ( 0, addr & 0x1FFF ) >> (addr >> 13);
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return t << 8 & 0x100;
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}
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//// Status flag handling
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// Hex value in name to clarify code and bit shifting.
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// Flag stored in indicated variable during emulation
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int const n80 = 0x80; // nz
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int const v40 = 0x40; // psw
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int const p20 = 0x20; // dp
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int const b10 = 0x10; // psw
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int const h08 = 0x08; // psw
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int const i04 = 0x04; // psw
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int const z02 = 0x02; // nz
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int const c01 = 0x01; // c
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int const nz_neg_mask = 0x880; // either bit set indicates N flag set
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#define GET_PSW( out )\
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{\
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out = psw & ~(n80 | p20 | z02 | c01);\
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out |= c >> 8 & c01;\
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out |= dp >> 3 & p20;\
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out |= ((nz >> 4) | nz) & n80;\
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if ( !(uint8_t) nz ) out |= z02;\
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}
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#define SET_PSW( in )\
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{\
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psw = in;\
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c = in << 8;\
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dp = in << 3 & 0x100;\
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nz = (in << 4 & 0x800) | (~in & z02);\
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}
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SPC_CPU_RUN_FUNC
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{
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uint8_t* const ram = RAM;
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uint8_t a = m.cpu_regs.a;
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uint8_t x = m.cpu_regs.x;
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uint8_t y = m.cpu_regs.y;
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uint16_t pc;
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uint8_t sp;
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int psw;
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int c;
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int nz;
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int dp;
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SET_PC( m.cpu_regs.pc );
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SET_SP( m.cpu_regs.sp );
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SET_PSW( m.cpu_regs.psw );
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goto loop;
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// Main loop
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cbranch_taken_loop:
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pc += (int8_t) ram [pc];
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inc_pc_loop:
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pc++;
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loop:
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{
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unsigned opcode;
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unsigned data;
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check( (unsigned) a < 0x100 );
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check( (unsigned) x < 0x100 );
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check( (unsigned) y < 0x100 );
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opcode = ram [pc];
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if ( (rel_time += m.cycle_table [opcode]) > 0 )
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goto out_of_time;
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#ifdef SPC_CPU_OPCODE_HOOK
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SPC_CPU_OPCODE_HOOK( GET_PC(), opcode );
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#endif
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/*
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//SUB_CASE_COUNTER( 1 );
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#define PROFILE_TIMER_LOOP( op, addr, len )\
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if ( opcode == op )\
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{\
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int cond = (unsigned) ((addr) - 0xFD) < 3 &&\
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pc [len] == 0xF0 && pc [len+1] == 0xFE - len;\
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SUB_CASE_COUNTER( op && cond );\
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}
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PROFILE_TIMER_LOOP( 0xEC, GET_LE16( pc + 1 ), 3 );
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PROFILE_TIMER_LOOP( 0xEB, pc [1], 2 );
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PROFILE_TIMER_LOOP( 0xE4, pc [1], 2 );
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*/
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// TODO: if PC is at end of memory, this will get wrong operand (very obscure)
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pc++;
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data = ram [pc];
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switch ( opcode )
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{
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// Common instructions
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#define BRANCH( cond )\
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{\
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pc++;\
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pc += (int8_t) data;\
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if ( cond )\
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goto loop;\
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pc -= (int8_t) data;\
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rel_time -= 2;\
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goto loop;\
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}
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case 0xF0: // BEQ
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BRANCH( !(uint8_t) nz ) // 89% taken
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case 0xD0: // BNE
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BRANCH( (uint8_t) nz )
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case 0x3F:{// CALL
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int old_addr = GET_PC() + 2;
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SET_PC( READ_PC16( pc ) );
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PUSH16( old_addr );
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goto loop;
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}
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case 0x6F:// RET
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{
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uint8_t l, h;
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POP( l );
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POP( h );
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SET_PC( l | (h << 8) );
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}
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goto loop;
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case 0xE4: // MOV a,dp
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++pc;
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// 80% from timer
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READ_DP_TIMER( 0, data, a = nz );
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goto loop;
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case 0xFA:{// MOV dp,dp
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int temp;
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READ_DP_TIMER( -2, data, temp );
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data = temp + no_read_before_write ;
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}
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// fall through
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case 0x8F:{// MOV dp,#imm
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int temp = READ_PC( pc + 1 );
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pc += 2;
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#if !SPC_MORE_ACCURACY
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{
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int i = dp + temp;
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ram [i] = (uint8_t) data;
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i -= 0xF0;
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if ( (unsigned) i < 0x10 ) // 76%
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{
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REGS [i] = (uint8_t) data;
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// Registers other than $F2 and $F4-$F7
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if ( i != 2 && (i < 4 || i > 7)) // 12%
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cpu_write_smp_reg( data, rel_time, i );
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}
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}
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#else
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WRITE_DP( 0, temp, data );
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#endif
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goto loop;
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}
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case 0xC4: // MOV dp,a
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++pc;
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#if !SPC_MORE_ACCURACY
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{
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int i = dp + data;
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ram [i] = (uint8_t) a;
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i -= 0xF0;
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if ( (unsigned) i < 0x10 ) // 39%
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{
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unsigned sel = i - 2;
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REGS [i] = (uint8_t) a;
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if ( sel == 1 ) // 51% $F3
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dsp_write( a, rel_time );
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else if ( sel > 1 ) // 1% not $F2 or $F3
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cpu_write_smp_reg_( a, rel_time, i );
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}
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}
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#else
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WRITE_DP( 0, data, a );
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#endif
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goto loop;
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#define CASE( n ) case n:
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// Define common address modes based on opcode for immediate mode. Execution
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// ends with data set to the address of the operand.
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#define ADDR_MODES_( op )\
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CASE( op - 0x02 ) /* (X) */\
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data = x + dp;\
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pc--;\
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goto end_##op;\
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CASE( op + 0x0F ) /* (dp)+Y */\
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data = READ_PROG16( data + dp ) + y;\
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goto end_##op;\
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CASE( op - 0x01 ) /* (dp+X) */\
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data = READ_PROG16( ((uint8_t) (data + x)) + dp );\
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goto end_##op;\
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CASE( op + 0x0E ) /* abs+Y */\
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data += y;\
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goto abs_##op;\
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CASE( op + 0x0D ) /* abs+X */\
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data += x;\
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CASE( op - 0x03 ) /* abs */\
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abs_##op:\
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data += 0x100 * READ_PC( ++pc );\
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goto end_##op;\
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CASE( op + 0x0C ) /* dp+X */\
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data = (uint8_t) (data + x);
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#define ADDR_MODES_NO_DP( op )\
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ADDR_MODES_( op )\
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data += dp;\
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end_##op:
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#define ADDR_MODES( op )\
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ADDR_MODES_( op )\
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CASE( op - 0x04 ) /* dp */\
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data += dp;\
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end_##op:
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// 1. 8-bit Data Transmission Commands. Group I
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ADDR_MODES_NO_DP( 0xE8 ) // MOV A,addr
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a = nz = READ( 0, data );
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goto inc_pc_loop;
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case 0xBF:{// MOV A,(X)+
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int temp = x + dp;
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x = (uint8_t) (x + 1);
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a = nz = READ( -1, temp );
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goto loop;
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}
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case 0xE8: // MOV A,imm
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a = data;
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nz = data;
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goto inc_pc_loop;
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case 0xF9: // MOV X,dp+Y
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data = (uint8_t) (data + y);
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case 0xF8: // MOV X,dp
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READ_DP_TIMER( 0, data, x = nz );
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goto inc_pc_loop;
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case 0xE9: // MOV X,abs
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data = READ_PC16( pc );
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++pc;
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data = READ( 0, data );
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case 0xCD: // MOV X,imm
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x = data;
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nz = data;
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goto inc_pc_loop;
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case 0xFB: // MOV Y,dp+X
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data = (uint8_t) (data + x);
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case 0xEB: // MOV Y,dp
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// 70% from timer
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pc++;
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READ_DP_TIMER( 0, data, y = nz );
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goto loop;
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case 0xEC:{// MOV Y,abs
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int temp = READ_PC16( pc );
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pc += 2;
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READ_TIMER( 0, temp, y = nz );
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//y = nz = READ( 0, temp );
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goto loop;
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}
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case 0x8D: // MOV Y,imm
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y = data;
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nz = data;
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goto inc_pc_loop;
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// 2. 8-BIT DATA TRANSMISSION COMMANDS, GROUP 2
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ADDR_MODES_NO_DP( 0xC8 ) // MOV addr,A
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WRITE( 0, data, a );
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goto inc_pc_loop;
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{
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int temp;
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case 0xCC: // MOV abs,Y
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temp = y;
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goto mov_abs_temp;
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case 0xC9: // MOV abs,X
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temp = x;
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mov_abs_temp:
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WRITE( 0, READ_PC16( pc ), temp );
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pc += 2;
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goto loop;
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}
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case 0xD9: // MOV dp+Y,X
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data = (uint8_t) (data + y);
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case 0xD8: // MOV dp,X
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WRITE( 0, data + dp, x );
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goto inc_pc_loop;
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case 0xDB: // MOV dp+X,Y
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data = (uint8_t) (data + x);
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case 0xCB: // MOV dp,Y
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WRITE( 0, data + dp, y );
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goto inc_pc_loop;
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// 3. 8-BIT DATA TRANSMISSIN COMMANDS, GROUP 3.
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case 0x7D: // MOV A,X
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a = x;
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nz = x;
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goto loop;
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case 0xDD: // MOV A,Y
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a = y;
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nz = y;
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goto loop;
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case 0x5D: // MOV X,A
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x = a;
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nz = a;
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goto loop;
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case 0xFD: // MOV Y,A
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y = a;
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nz = a;
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goto loop;
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case 0x9D: // MOV X,SP
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x = nz = GET_SP();
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goto loop;
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case 0xBD: // MOV SP,X
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SET_SP( x );
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goto loop;
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//case 0xC6: // MOV (X),A (handled by MOV addr,A in group 2)
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case 0xAF: // MOV (X)+,A
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WRITE_DP( 0, x, a + no_read_before_write );
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x = (uint8_t) (x + 1);
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goto loop;
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// 5. 8-BIT LOGIC OPERATION COMMANDS
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#define LOGICAL_OP( op, func )\
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ADDR_MODES( op ) /* addr */\
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data = READ( 0, data );\
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case op: /* imm */\
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nz = a func##= data;\
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goto inc_pc_loop;\
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{ unsigned addr;\
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case op + 0x11: /* X,Y */\
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data = READ_DP( -2, y );\
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addr = x + dp;\
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goto addr_##op;\
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case op + 0x01: /* dp,dp */\
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data = READ_DP( -3, data );\
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case op + 0x10:{/*dp,imm*/\
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uint16_t addr2 = pc + 1;\
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pc += 2;\
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addr = READ_PC( addr2 ) + dp;\
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}\
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addr_##op:\
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nz = data func READ( -1, addr );\
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WRITE( 0, addr, nz );\
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goto loop;\
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}
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LOGICAL_OP( 0x28, & ); // AND
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LOGICAL_OP( 0x08, | ); // OR
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LOGICAL_OP( 0x48, ^ ); // EOR
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// 4. 8-BIT ARITHMETIC OPERATION COMMANDS
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ADDR_MODES( 0x68 ) // CMP addr
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data = READ( 0, data );
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case 0x68: // CMP imm
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nz = a - data;
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c = ~nz;
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nz &= 0xFF;
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goto inc_pc_loop;
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case 0x79: // CMP (X),(Y)
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data = READ_DP( -2, y );
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nz = READ_DP( -1, x ) - data;
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c = ~nz;
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nz &= 0xFF;
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goto loop;
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case 0x69: // CMP dp,dp
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data = READ_DP( -3, data );
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case 0x78: // CMP dp,imm
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nz = READ_DP( -1, READ_PC( ++pc ) ) - data;
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c = ~nz;
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nz &= 0xFF;
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goto inc_pc_loop;
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case 0x3E: // CMP X,dp
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data += dp;
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goto cmp_x_addr;
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case 0x1E: // CMP X,abs
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data = READ_PC16( pc );
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pc++;
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cmp_x_addr:
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data = READ( 0, data );
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case 0xC8: // CMP X,imm
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nz = x - data;
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c = ~nz;
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nz &= 0xFF;
|
|
goto inc_pc_loop;
|
|
|
|
case 0x7E: // CMP Y,dp
|
|
data += dp;
|
|
goto cmp_y_addr;
|
|
case 0x5E: // CMP Y,abs
|
|
data = READ_PC16( pc );
|
|
pc++;
|
|
cmp_y_addr:
|
|
data = READ( 0, data );
|
|
case 0xAD: // CMP Y,imm
|
|
nz = y - data;
|
|
c = ~nz;
|
|
nz &= 0xFF;
|
|
goto inc_pc_loop;
|
|
|
|
{
|
|
int addr;
|
|
case 0xB9: // SBC (x),(y)
|
|
case 0x99: // ADC (x),(y)
|
|
pc--; // compensate for inc later
|
|
data = READ_DP( -2, y );
|
|
addr = x + dp;
|
|
goto adc_addr;
|
|
case 0xA9: // SBC dp,dp
|
|
case 0x89: // ADC dp,dp
|
|
data = READ_DP( -3, data );
|
|
case 0xB8: // SBC dp,imm
|
|
case 0x98: // ADC dp,imm
|
|
addr = READ_PC( ++pc ) + dp;
|
|
adc_addr:
|
|
nz = READ( -1, addr );
|
|
goto adc_data;
|
|
|
|
// catch ADC and SBC together, then decode later based on operand
|
|
#undef CASE
|
|
#define CASE( n ) case n: case (n) + 0x20:
|
|
ADDR_MODES( 0x88 ) // ADC/SBC addr
|
|
data = READ( 0, data );
|
|
case 0xA8: // SBC imm
|
|
case 0x88: // ADC imm
|
|
addr = -1; // A
|
|
nz = a;
|
|
adc_data: {
|
|
int flags;
|
|
if ( opcode >= 0xA0 ) // SBC
|
|
data ^= 0xFF;
|
|
|
|
flags = data ^ nz;
|
|
nz += data + (c >> 8 & 1);
|
|
flags ^= nz;
|
|
|
|
psw = (psw & ~(v40 | h08)) |
|
|
(flags >> 1 & h08) |
|
|
((flags + 0x80) >> 2 & v40);
|
|
c = nz;
|
|
if ( addr < 0 )
|
|
{
|
|
a = (uint8_t) nz;
|
|
goto inc_pc_loop;
|
|
}
|
|
WRITE( 0, addr, /*(uint8_t)*/ nz );
|
|
goto inc_pc_loop;
|
|
}
|
|
|
|
}
|
|
|
|
// 6. ADDITION & SUBTRACTION COMMANDS
|
|
|
|
#define INC_DEC_REG( reg, op )\
|
|
nz = reg op;\
|
|
reg = (uint8_t) nz;\
|
|
goto loop;
|
|
|
|
case 0xBC: INC_DEC_REG( a, + 1 ) // INC A
|
|
case 0x3D: INC_DEC_REG( x, + 1 ) // INC X
|
|
case 0xFC: INC_DEC_REG( y, + 1 ) // INC Y
|
|
|
|
case 0x9C: INC_DEC_REG( a, - 1 ) // DEC A
|
|
case 0x1D: INC_DEC_REG( x, - 1 ) // DEC X
|
|
case 0xDC: INC_DEC_REG( y, - 1 ) // DEC Y
|
|
|
|
case 0x9B: // DEC dp+X
|
|
case 0xBB: // INC dp+X
|
|
data = (uint8_t) (data + x);
|
|
case 0x8B: // DEC dp
|
|
case 0xAB: // INC dp
|
|
data += dp;
|
|
goto inc_abs;
|
|
case 0x8C: // DEC abs
|
|
case 0xAC: // INC abs
|
|
data = READ_PC16( pc );
|
|
pc++;
|
|
inc_abs:
|
|
nz = (opcode >> 4 & 2) - 1;
|
|
nz += READ( -1, data );
|
|
WRITE( 0, data, /*(uint8_t)*/ nz );
|
|
goto inc_pc_loop;
|
|
|
|
// 7. SHIFT, ROTATION COMMANDS
|
|
|
|
case 0x5C: // LSR A
|
|
c = 0;
|
|
case 0x7C:{// ROR A
|
|
nz = (c >> 1 & 0x80) | (a >> 1);
|
|
c = a << 8;
|
|
a = nz;
|
|
goto loop;
|
|
}
|
|
|
|
case 0x1C: // ASL A
|
|
c = 0;
|
|
case 0x3C:{// ROL A
|
|
int temp = c >> 8 & 1;
|
|
c = a << 1;
|
|
nz = c | temp;
|
|
a = (uint8_t) nz;
|
|
goto loop;
|
|
}
|
|
|
|
case 0x0B: // ASL dp
|
|
c = 0;
|
|
data += dp;
|
|
goto rol_mem;
|
|
case 0x1B: // ASL dp+X
|
|
c = 0;
|
|
case 0x3B: // ROL dp+X
|
|
data = (uint8_t) (data + x);
|
|
case 0x2B: // ROL dp
|
|
data += dp;
|
|
goto rol_mem;
|
|
case 0x0C: // ASL abs
|
|
c = 0;
|
|
case 0x2C: // ROL abs
|
|
data = READ_PC16( pc );
|
|
pc++;
|
|
rol_mem:
|
|
nz = c >> 8 & 1;
|
|
nz |= (c = READ( -1, data ) << 1);
|
|
WRITE( 0, data, /*(uint8_t)*/ nz );
|
|
goto inc_pc_loop;
|
|
|
|
case 0x4B: // LSR dp
|
|
c = 0;
|
|
data += dp;
|
|
goto ror_mem;
|
|
case 0x5B: // LSR dp+X
|
|
c = 0;
|
|
case 0x7B: // ROR dp+X
|
|
data = (uint8_t) (data + x);
|
|
case 0x6B: // ROR dp
|
|
data += dp;
|
|
goto ror_mem;
|
|
case 0x4C: // LSR abs
|
|
c = 0;
|
|
case 0x6C: // ROR abs
|
|
data = READ_PC16( pc );
|
|
pc++;
|
|
ror_mem: {
|
|
int temp = READ( -1, data );
|
|
nz = (c >> 1 & 0x80) | (temp >> 1);
|
|
c = temp << 8;
|
|
WRITE( 0, data, nz );
|
|
goto inc_pc_loop;
|
|
}
|
|
|
|
case 0x9F: // XCN
|
|
nz = a = (a >> 4) | (uint8_t) (a << 4);
|
|
goto loop;
|
|
|
|
// 8. 16-BIT TRANSMISION COMMANDS
|
|
|
|
case 0xBA: // MOVW YA,dp
|
|
a = READ_DP( -2, data );
|
|
nz = (a & 0x7F) | (a >> 1);
|
|
y = READ_DP( 0, (uint8_t) (data + 1) );
|
|
nz |= y;
|
|
goto inc_pc_loop;
|
|
|
|
case 0xDA: // MOVW dp,YA
|
|
WRITE_DP( -1, data, a );
|
|
WRITE_DP( 0, (uint8_t) (data + 1), y + no_read_before_write );
|
|
goto inc_pc_loop;
|
|
|
|
// 9. 16-BIT OPERATION COMMANDS
|
|
|
|
case 0x3A: // INCW dp
|
|
case 0x1A:{// DECW dp
|
|
int temp;
|
|
// low byte
|
|
data += dp;
|
|
temp = READ( -3, data );
|
|
temp += (opcode >> 4 & 2) - 1; // +1 for INCW, -1 for DECW
|
|
nz = ((temp >> 1) | temp) & 0x7F;
|
|
WRITE( -2, data, /*(uint8_t)*/ temp );
|
|
|
|
// high byte
|
|
data = (uint8_t) (data + 1) + dp;
|
|
temp = (uint8_t) ((temp >> 8) + READ( -1, data ));
|
|
nz |= temp;
|
|
WRITE( 0, data, temp );
|
|
|
|
goto inc_pc_loop;
|
|
}
|
|
|
|
case 0x7A: // ADDW YA,dp
|
|
case 0x9A:{// SUBW YA,dp
|
|
int lo = READ_DP( -2, data );
|
|
int hi = READ_DP( 0, (uint8_t) (data + 1) );
|
|
int result;
|
|
int flags;
|
|
|
|
if ( opcode == 0x9A ) // SUBW
|
|
{
|
|
lo = (lo ^ 0xFF) + 1;
|
|
hi ^= 0xFF;
|
|
}
|
|
|
|
lo += a;
|
|
result = y + hi + (lo >> 8);
|
|
flags = hi ^ y ^ result;
|
|
|
|
psw = (psw & ~(v40 | h08)) |
|
|
(flags >> 1 & h08) |
|
|
((flags + 0x80) >> 2 & v40);
|
|
c = result;
|
|
a = (uint8_t) lo;
|
|
result = (uint8_t) result;
|
|
y = result;
|
|
nz = (((lo >> 1) | lo) & 0x7F) | result;
|
|
|
|
goto inc_pc_loop;
|
|
}
|
|
|
|
case 0x5A: { // CMPW YA,dp
|
|
int temp = a - READ_DP( -1, data );
|
|
nz = ((temp >> 1) | temp) & 0x7F;
|
|
temp = y + (temp >> 8);
|
|
temp -= READ_DP( 0, (uint8_t) (data + 1) );
|
|
nz |= temp;
|
|
c = ~temp;
|
|
nz &= 0xFF;
|
|
goto inc_pc_loop;
|
|
}
|
|
|
|
// 10. MULTIPLICATION & DIVISON COMMANDS
|
|
|
|
case 0xCF: { // MUL YA
|
|
unsigned temp = y * a;
|
|
a = (uint8_t) temp;
|
|
nz = ((temp >> 1) | temp) & 0x7F;
|
|
y = (uint8_t) (temp >> 8);
|
|
nz |= y;
|
|
goto loop;
|
|
}
|
|
|
|
case 0x9E: // DIV YA,X
|
|
{
|
|
unsigned ya = y * 0x100 + a;
|
|
|
|
psw &= ~(h08 | v40);
|
|
|
|
if ( y >= x )
|
|
psw |= v40;
|
|
|
|
if ( (y & 15) >= (x & 15) )
|
|
psw |= h08;
|
|
|
|
if ( y < x * 2 )
|
|
{
|
|
a = ya / x;
|
|
y = ya - a * x;
|
|
}
|
|
else
|
|
{
|
|
a = 255 - (ya - x * 0x200) / (256 - x);
|
|
y = x + (ya - x * 0x200) % (256 - x);
|
|
}
|
|
|
|
nz = (uint8_t) a;
|
|
a = (uint8_t) a;
|
|
y = (uint8_t) y;
|
|
|
|
goto loop;
|
|
}
|
|
|
|
// 11. DECIMAL COMPENSATION COMMANDS
|
|
|
|
case 0xDF: // DAA
|
|
SUSPICIOUS_OPCODE( "DAA" );
|
|
if ( a > 0x99 || c & 0x100 )
|
|
{
|
|
a += 0x60;
|
|
c = 0x100;
|
|
}
|
|
|
|
if ( (a & 0x0F) > 9 || psw & h08 )
|
|
a += 0x06;
|
|
|
|
nz = a;
|
|
a = (uint8_t) a;
|
|
goto loop;
|
|
|
|
case 0xBE: // DAS
|
|
SUSPICIOUS_OPCODE( "DAS" );
|
|
if ( a > 0x99 || !(c & 0x100) )
|
|
{
|
|
a -= 0x60;
|
|
c = 0;
|
|
}
|
|
|
|
if ( (a & 0x0F) > 9 || !(psw & h08) )
|
|
a -= 0x06;
|
|
|
|
nz = a;
|
|
a = (uint8_t) a;
|
|
goto loop;
|
|
|
|
// 12. BRANCHING COMMANDS
|
|
|
|
case 0x2F: // BRA rel
|
|
pc += (int8_t) data;
|
|
goto inc_pc_loop;
|
|
|
|
case 0x30: // BMI
|
|
BRANCH( (nz & nz_neg_mask) )
|
|
|
|
case 0x10: // BPL
|
|
BRANCH( !(nz & nz_neg_mask) )
|
|
|
|
case 0xB0: // BCS
|
|
BRANCH( c & 0x100 )
|
|
|
|
case 0x90: // BCC
|
|
BRANCH( !(c & 0x100) )
|
|
|
|
case 0x70: // BVS
|
|
BRANCH( psw & v40 )
|
|
|
|
case 0x50: // BVC
|
|
BRANCH( !(psw & v40) )
|
|
|
|
#define CBRANCH( cond )\
|
|
{\
|
|
pc++;\
|
|
if ( cond )\
|
|
goto cbranch_taken_loop;\
|
|
rel_time -= 2;\
|
|
goto inc_pc_loop;\
|
|
}
|
|
|
|
case 0x03: // BBS dp.bit,rel
|
|
case 0x23:
|
|
case 0x43:
|
|
case 0x63:
|
|
case 0x83:
|
|
case 0xA3:
|
|
case 0xC3:
|
|
case 0xE3:
|
|
CBRANCH( READ_DP( -4, data ) >> (opcode >> 5) & 1 )
|
|
|
|
case 0x13: // BBC dp.bit,rel
|
|
case 0x33:
|
|
case 0x53:
|
|
case 0x73:
|
|
case 0x93:
|
|
case 0xB3:
|
|
case 0xD3:
|
|
case 0xF3:
|
|
CBRANCH( !(READ_DP( -4, data ) >> (opcode >> 5) & 1) )
|
|
|
|
case 0xDE: // CBNE dp+X,rel
|
|
data = (uint8_t) (data + x);
|
|
// fall through
|
|
case 0x2E:{// CBNE dp,rel
|
|
int temp;
|
|
// 61% from timer
|
|
READ_DP_TIMER( -4, data, temp );
|
|
CBRANCH( temp != a )
|
|
}
|
|
|
|
case 0x6E: { // DBNZ dp,rel
|
|
unsigned temp = READ_DP( -4, data ) - 1;
|
|
WRITE_DP( -3, (uint8_t) data, /*(uint8_t)*/ temp + no_read_before_write );
|
|
CBRANCH( temp )
|
|
}
|
|
|
|
case 0xFE: // DBNZ Y,rel
|
|
y = (uint8_t) (y - 1);
|
|
BRANCH( y )
|
|
|
|
case 0x1F: // JMP [abs+X]
|
|
SET_PC( READ_PC16( pc ) + x );
|
|
// fall through
|
|
case 0x5F: // JMP abs
|
|
SET_PC( READ_PC16( pc ) );
|
|
goto loop;
|
|
|
|
// 13. SUB-ROUTINE CALL RETURN COMMANDS
|
|
|
|
case 0x0F:{// BRK
|
|
int temp;
|
|
int ret_addr = GET_PC();
|
|
SUSPICIOUS_OPCODE( "BRK" );
|
|
SET_PC( READ_PROG16( 0xFFDE ) ); // vector address verified
|
|
PUSH16( ret_addr );
|
|
GET_PSW( temp );
|
|
psw = (psw | b10) & ~i04;
|
|
PUSH( temp );
|
|
goto loop;
|
|
}
|
|
|
|
case 0x4F:{// PCALL offset
|
|
int ret_addr = GET_PC() + 1;
|
|
SET_PC( 0xFF00 | data );
|
|
PUSH16( ret_addr );
|
|
goto loop;
|
|
}
|
|
|
|
case 0x01: // TCALL n
|
|
case 0x11:
|
|
case 0x21:
|
|
case 0x31:
|
|
case 0x41:
|
|
case 0x51:
|
|
case 0x61:
|
|
case 0x71:
|
|
case 0x81:
|
|
case 0x91:
|
|
case 0xA1:
|
|
case 0xB1:
|
|
case 0xC1:
|
|
case 0xD1:
|
|
case 0xE1:
|
|
case 0xF1: {
|
|
int ret_addr = GET_PC();
|
|
SET_PC( READ_PROG16( 0xFFDE - (opcode >> 3) ) );
|
|
PUSH16( ret_addr );
|
|
goto loop;
|
|
}
|
|
|
|
// 14. STACK OPERATION COMMANDS
|
|
|
|
{
|
|
int temp;
|
|
uint8_t l, h;
|
|
case 0x7F: // RET1
|
|
POP (temp);
|
|
POP (l);
|
|
POP (h);
|
|
SET_PC( l | (h << 8) );
|
|
goto set_psw;
|
|
case 0x8E: // POP PSW
|
|
POP( temp );
|
|
set_psw:
|
|
SET_PSW( temp );
|
|
goto loop;
|
|
}
|
|
|
|
case 0x0D: { // PUSH PSW
|
|
int temp;
|
|
GET_PSW( temp );
|
|
PUSH( temp );
|
|
goto loop;
|
|
}
|
|
|
|
case 0x2D: // PUSH A
|
|
PUSH( a );
|
|
goto loop;
|
|
|
|
case 0x4D: // PUSH X
|
|
PUSH( x );
|
|
goto loop;
|
|
|
|
case 0x6D: // PUSH Y
|
|
PUSH( y );
|
|
goto loop;
|
|
|
|
case 0xAE: // POP A
|
|
POP( a );
|
|
goto loop;
|
|
|
|
case 0xCE: // POP X
|
|
POP( x );
|
|
goto loop;
|
|
|
|
case 0xEE: // POP Y
|
|
POP( y );
|
|
goto loop;
|
|
|
|
// 15. BIT OPERATION COMMANDS
|
|
|
|
case 0x02: // SET1
|
|
case 0x22:
|
|
case 0x42:
|
|
case 0x62:
|
|
case 0x82:
|
|
case 0xA2:
|
|
case 0xC2:
|
|
case 0xE2:
|
|
case 0x12: // CLR1
|
|
case 0x32:
|
|
case 0x52:
|
|
case 0x72:
|
|
case 0x92:
|
|
case 0xB2:
|
|
case 0xD2:
|
|
case 0xF2: {
|
|
int bit = 1 << (opcode >> 5);
|
|
int mask = ~bit;
|
|
if ( opcode & 0x10 )
|
|
bit = 0;
|
|
data += dp;
|
|
WRITE( 0, data, (READ( -1, data ) & mask) | bit );
|
|
goto inc_pc_loop;
|
|
}
|
|
|
|
case 0x0E: // TSET1 abs
|
|
case 0x4E: // TCLR1 abs
|
|
data = READ_PC16( pc );
|
|
pc += 2;
|
|
{
|
|
unsigned temp = READ( -2, data );
|
|
nz = (uint8_t) (a - temp);
|
|
temp &= ~a;
|
|
if ( opcode == 0x0E )
|
|
temp |= a;
|
|
WRITE( 0, data, temp );
|
|
}
|
|
goto loop;
|
|
|
|
case 0x4A: // AND1 C,mem.bit
|
|
c &= MEM_BIT( 0 );
|
|
pc += 2;
|
|
goto loop;
|
|
|
|
case 0x6A: // AND1 C,/mem.bit
|
|
c &= ~MEM_BIT( 0 );
|
|
pc += 2;
|
|
goto loop;
|
|
|
|
case 0x0A: // OR1 C,mem.bit
|
|
c |= MEM_BIT( -1 );
|
|
pc += 2;
|
|
goto loop;
|
|
|
|
case 0x2A: // OR1 C,/mem.bit
|
|
c |= ~MEM_BIT( -1 );
|
|
pc += 2;
|
|
goto loop;
|
|
|
|
case 0x8A: // EOR1 C,mem.bit
|
|
c ^= MEM_BIT( -1 );
|
|
pc += 2;
|
|
goto loop;
|
|
|
|
case 0xEA: // NOT1 mem.bit
|
|
data = READ_PC16( pc );
|
|
pc += 2;
|
|
{
|
|
unsigned temp = READ( -1, data & 0x1FFF );
|
|
temp ^= 1 << (data >> 13);
|
|
WRITE( 0, data & 0x1FFF, temp );
|
|
}
|
|
goto loop;
|
|
|
|
case 0xCA: // MOV1 mem.bit,C
|
|
data = READ_PC16( pc );
|
|
pc += 2;
|
|
{
|
|
unsigned temp = READ( -2, data & 0x1FFF );
|
|
unsigned bit = data >> 13;
|
|
temp = (temp & ~(1 << bit)) | ((c >> 8 & 1) << bit);
|
|
WRITE( 0, data & 0x1FFF, temp + no_read_before_write );
|
|
}
|
|
goto loop;
|
|
|
|
case 0xAA: // MOV1 C,mem.bit
|
|
c = MEM_BIT( 0 );
|
|
pc += 2;
|
|
goto loop;
|
|
|
|
// 16. PROGRAM PSW FLAG OPERATION COMMANDS
|
|
|
|
case 0x60: // CLRC
|
|
c = 0;
|
|
goto loop;
|
|
|
|
case 0x80: // SETC
|
|
c = ~0;
|
|
goto loop;
|
|
|
|
case 0xED: // NOTC
|
|
c ^= 0x100;
|
|
goto loop;
|
|
|
|
case 0xE0: // CLRV
|
|
psw &= ~(v40 | h08);
|
|
goto loop;
|
|
|
|
case 0x20: // CLRP
|
|
dp = 0;
|
|
goto loop;
|
|
|
|
case 0x40: // SETP
|
|
dp = 0x100;
|
|
goto loop;
|
|
|
|
case 0xA0: // EI
|
|
SUSPICIOUS_OPCODE( "EI" );
|
|
psw |= i04;
|
|
goto loop;
|
|
|
|
case 0xC0: // DI
|
|
SUSPICIOUS_OPCODE( "DI" );
|
|
psw &= ~i04;
|
|
goto loop;
|
|
|
|
// 17. OTHER COMMANDS
|
|
|
|
case 0x00: // NOP
|
|
goto loop;
|
|
|
|
case 0xFF:{// STOP
|
|
// handle PC wrap-around
|
|
if ( pc == 0x0000 )
|
|
{
|
|
debug_printf( "SPC: PC wrapped around\n" );
|
|
goto loop;
|
|
}
|
|
}
|
|
// fall through
|
|
case 0xEF: // SLEEP
|
|
SUSPICIOUS_OPCODE( "STOP/SLEEP" );
|
|
--pc;
|
|
rel_time = 0;
|
|
m.cpu_error = "SPC emulation error";
|
|
goto stop;
|
|
} // switch
|
|
|
|
assert( 0 ); // catch any unhandled instructions
|
|
}
|
|
out_of_time:
|
|
rel_time -= m.cycle_table [ ram [pc] ]; // undo partial execution of opcode
|
|
stop:
|
|
|
|
// Uncache registers
|
|
m.cpu_regs.pc = (uint16_t) GET_PC();
|
|
m.cpu_regs.sp = ( uint8_t) GET_SP();
|
|
m.cpu_regs.a = ( uint8_t) a;
|
|
m.cpu_regs.x = ( uint8_t) x;
|
|
m.cpu_regs.y = ( uint8_t) y;
|
|
{
|
|
int temp;
|
|
GET_PSW( temp );
|
|
m.cpu_regs.psw = (uint8_t) temp;
|
|
}
|
|
}
|
|
SPC_CPU_RUN_FUNC_END
|