mirror of
https://github.com/ZDoom/qzdoom.git
synced 2025-02-08 16:52:01 +00:00
Finish Vector4 implementation
This commit is contained in:
RaveYard
Christoph Oelckers
parent
a525233914
commit
31db5847cc
15 changed files with 326 additions and 196 deletions
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@ -484,12 +484,15 @@ int EncodeRegType(ExpEmit reg)
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else if (reg.RegCount == 2)
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{
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regtype |= REGT_MULTIREG2;
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}
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else if (reg.RegCount == 3)
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{
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regtype |= REGT_MULTIREG3;
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}
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else if (reg.RegCount == 4)
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{
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regtype |= REGT_MULTIREG4;
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}
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return regtype;
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}
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@ -596,6 +599,7 @@ FxExpression *FxVectorValue::Resolve(FCompileContext&ctx)
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{
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bool fails = false;
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// Cast every scalar to float64
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for (auto &a : xyzw)
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{
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if (a != nullptr)
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@ -604,7 +608,7 @@ FxExpression *FxVectorValue::Resolve(FCompileContext&ctx)
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if (a == nullptr) fails = true;
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else
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{
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if (a->ValueType != TypeVector2) // a vec3 may be initialized with (vec2, z)
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if (a->ValueType != TypeVector2 && a->ValueType != TypeVector3) // smaller vector can be used to initialize another vector
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{
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a = new FxFloatCast(a);
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a = a->Resolve(ctx);
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@ -613,59 +617,80 @@ FxExpression *FxVectorValue::Resolve(FCompileContext&ctx)
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}
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}
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}
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if (fails)
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{
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delete this;
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return nullptr;
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}
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// at this point there are five legal cases:
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// * two floats = vector2
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// * three floats = vector3
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// * four floats = vector4
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// * vector2 + float = vector3
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// * vector3 + float = vector4
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if (xyzw[0]->ValueType == TypeVector2)
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// The actual dimension of the Vector does not correspond to the amount of non-null elements in xyzw
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// For example: '(asdf.xy, 1)' would be Vector3 where xyzw[0]->ValueType == TypeVector2 and xyzw[1]->ValueType == TypeFloat64
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// Handle nesting and figure out the dimension of the vector
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int vectorDimensions = 0;
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for (int i = 0; i < maxVectorDimensions && xyzw[i]; ++i)
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{
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if (xyzw[1]->ValueType != TypeFloat64 || xyzw[2] != nullptr)
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assert(dynamic_cast<FxExpression*>(xyzw[i]));
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if (xyzw[i]->ValueType == TypeFloat64)
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{
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vectorDimensions++;
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}
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else if (xyzw[i]->ValueType == TypeVector2 || xyzw[i]->ValueType == TypeVector3 || xyzw[i]->ValueType == TypeVector4)
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{
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// Solve nested vector
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int regCount = xyzw[i]->ValueType->RegCount;
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if (regCount + vectorDimensions > maxVectorDimensions)
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{
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vectorDimensions += regCount; // Show proper number
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goto too_big;
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}
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// Nested initializer gets simplified
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if (xyzw[i]->ExprType == EFX_VectorValue)
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{
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// Shifts current elements to leave space for unwrapping nested initialization
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for (int l = maxVectorDimensions - 1; l > i; --l)
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{
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xyzw[l] = xyzw[l - regCount + 1];
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}
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auto vi = static_cast<FxVectorValue*>(xyzw[i]);
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for (int j = 0; j < regCount; ++j)
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{
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xyzw[i + j] = vi->xyzw[j];
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vi->xyzw[j] = nullptr; // Preserve object after 'delete vi;'
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}
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delete vi;
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// We extracted something, let's iterate on that again:
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--i;
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continue;
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}
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else
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{
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vectorDimensions += regCount;
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}
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}
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else
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{
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ScriptPosition.Message(MSG_ERROR, "Not a valid vector");
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delete this;
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return nullptr;
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}
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ValueType = TypeVector3;
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if (xyzw[0]->ExprType == EFX_VectorValue)
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{
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// If two vector initializers are nested, unnest them now.
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auto vi = static_cast<FxVectorValue*>(xyzw[0]);
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xyzw[2] = xyzw[1];
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xyzw[1] = vi->xyzw[1];
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xyzw[0] = vi->xyzw[0];
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vi->xyzw[0] = vi->xyzw[1] = nullptr; // Don't delete our own expressions.
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delete vi;
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}
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ValueType = TypeVector4;
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if (xyzw[0]->ExprType == EFX_VectorValue)
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{
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// If two vector initializers are nested, unnest them now.
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auto vi = static_cast<FxVectorValue*>(xyzw[0]);
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xyzw[2] = xyzw[1];
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xyzw[1] = vi->xyzw[1];
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xyzw[0] = vi->xyzw[0];
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vi->xyzw[0] = vi->xyzw[1] = nullptr; // Don't delete our own expressions.
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delete vi;
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}
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}
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else if (xyzw[0]->ValueType == TypeFloat64 && xyzw[1]->ValueType == TypeFloat64)
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switch (vectorDimensions)
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{
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ValueType = xyzw[2] == nullptr ? TypeVector2 : TypeVector3;
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}
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else if (xyzw[0]->ValueType == TypeFloat64 && xyzw[1]->ValueType == TypeFloat64 && xyzw[2]->ValueType == TypeFloat64)
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{
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ValueType = xyzw[3] == nullptr ? TypeVector3 : TypeVector4;
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}
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else
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{
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ScriptPosition.Message(MSG_ERROR, "Not a valid vector");
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case 2: ValueType = TypeVector2; break;
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case 3: ValueType = TypeVector3; break;
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case 4: ValueType = TypeVector4; break;
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default:
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too_big:;
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ScriptPosition.Message(MSG_ERROR, "Vector of %d dimensions is not supported", vectorDimensions);
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delete this;
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return nullptr;
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}
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@ -674,7 +699,7 @@ FxExpression *FxVectorValue::Resolve(FCompileContext&ctx)
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isConst = true;
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for (auto &a : xyzw)
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{
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if (a != nullptr && !a->isConstant()) isConst = false;
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if (a && !a->isConstant()) isConst = false;
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}
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return this;
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}
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@ -692,145 +717,96 @@ static ExpEmit EmitKonst(VMFunctionBuilder *build, ExpEmit &emit)
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ExpEmit FxVectorValue::Emit(VMFunctionBuilder *build)
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{
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// no const handling here. Ultimately it's too rarely used (i.e. the only fully constant vector ever allocated in ZDoom is the 0-vector in a very few places)
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// and the negatives (excessive allocation of float constants) outweigh the positives (saved a few instructions)
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assert(xyzw[0] != nullptr);
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assert(xyzw[1] != nullptr);
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if (ValueType == TypeVector2)
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int vectorDimensions = ValueType->RegCount;
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int vectorElements = 0;
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for (auto& e : xyzw)
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{
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ExpEmit tempxval = xyzw[0]->Emit(build);
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ExpEmit tempyval = xyzw[1]->Emit(build);
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ExpEmit xval = EmitKonst(build, tempxval);
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ExpEmit yval = EmitKonst(build, tempyval);
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assert(xval.RegType == REGT_FLOAT && yval.RegType == REGT_FLOAT);
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if (yval.RegNum == xval.RegNum + 1)
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{
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// The results are already in two continuous registers so just return them as-is.
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xval.RegCount++;
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return xval;
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}
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else
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{
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// The values are not in continuous registers so they need to be copied together now.
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ExpEmit out(build, REGT_FLOAT, 2);
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build->Emit(OP_MOVEF, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 1, yval.RegNum);
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xval.Free(build);
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yval.Free(build);
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return out;
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}
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if (e) vectorElements++;
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}
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else if (xyzw[0]->ValueType == TypeVector2) // vec2+float
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assert(vectorElements > 0);
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ExpEmit* tempVal = (ExpEmit*)calloc(vectorElements, sizeof(ExpEmit));
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ExpEmit* val = (ExpEmit*)calloc(vectorElements, sizeof(ExpEmit));
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// Init ExpEmit
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for (int i = 0; i < vectorElements; ++i)
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{
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ExpEmit xyval = xyzw[0]->Emit(build);
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ExpEmit tempzval = xyzw[1]->Emit(build);
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ExpEmit zval = EmitKonst(build, tempzval);
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assert(xyval.RegType == REGT_FLOAT && xyval.RegCount == 2 && zval.RegType == REGT_FLOAT);
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if (zval.RegNum == xyval.RegNum + 2)
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{
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// The results are already in three continuous registers so just return them as-is.
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xyval.RegCount++;
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return xyval;
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}
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else
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{
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// The values are not in continuous registers so they need to be copied together now.
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ExpEmit out(build, REGT_FLOAT, 4);
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build->Emit(OP_MOVEV2, out.RegNum, xyval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 2, zval.RegNum);
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xyval.Free(build);
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zval.Free(build);
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return out;
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}
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new(tempVal + i) ExpEmit(xyzw[i]->Emit(build));
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new(val + i) ExpEmit(EmitKonst(build, tempVal[i]));
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}
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else if (xyzw[0]->ValueType == TypeVector3) // vec3+float
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{
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assert(xyzw[2] != nullptr);
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ExpEmit tempxval = xyzw[0]->Emit(build);
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ExpEmit tempyval = xyzw[1]->Emit(build);
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ExpEmit tempzval = xyzw[2]->Emit(build);
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ExpEmit xval = EmitKonst(build, tempxval);
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ExpEmit yval = EmitKonst(build, tempyval);
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ExpEmit zval = EmitKonst(build, tempzval);
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assert(xval.RegType == REGT_FLOAT && yval.RegType == REGT_FLOAT && zval.RegType == REGT_FLOAT);
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if (yval.RegNum == xval.RegNum + 1 && zval.RegNum == xval.RegNum + 2)
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bool isContinuous = true;
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for (int i = 1; i < vectorElements; ++i)
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{
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// The results are already in three continuous registers so just return them as-is.
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xval.RegCount += 2;
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return xval;
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}
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else
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{
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// The values are not in continuous registers so they need to be copied together now.
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ExpEmit out(build, REGT_FLOAT, 4);
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//Try to optimize a bit...
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if (yval.RegNum == xval.RegNum + 1)
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if (val[i - 1].RegNum + val[i - 1].RegCount != val[i].RegNum)
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{
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build->Emit(OP_MOVEV2, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 2, zval.RegNum);
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isContinuous = false;
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break;
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}
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else if (zval.RegNum == yval.RegNum + 1)
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}
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// all values are in continuous registers:
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if (isContinuous)
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{
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val[0].RegCount = vectorDimensions;
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return val[0];
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}
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}
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ExpEmit out(build, REGT_FLOAT, vectorDimensions);
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{
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auto emitRegMove = [&](int regsToMove, int dstRegIndex, int srcRegIndex) {
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assert(dstRegIndex < vectorDimensions);
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assert(srcRegIndex < vectorDimensions);
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assert(regsToMove > 0 && regsToMove <= 4);
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build->Emit(regsToMove == 1 ? OP_MOVEF : OP_MOVEV2 + regsToMove - 2, out.RegNum + dstRegIndex, val[srcRegIndex].RegNum);
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static_assert(OP_MOVEV2 + 1 == OP_MOVEV3);
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static_assert(OP_MOVEV3 + 1 == OP_MOVEV4);
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};
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int regsToPush = 0;
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int nextRegNum = val[0].RegNum;
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int lastElementIndex = 0;
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int reg = 0;
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// Use larger MOVE OPs for any groups of registers that are continuous including those across individual xyzw[] elements
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for (int elementIndex = 0; elementIndex < vectorElements; ++elementIndex)
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{
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int regCount = xyzw[elementIndex]->ValueType->RegCount;
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if (nextRegNum != val[elementIndex].RegNum)
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{
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build->Emit(OP_MOVEF, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEV2, out.RegNum+1, yval.RegNum);
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emitRegMove(regsToPush, reg, lastElementIndex);
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reg += regsToPush;
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regsToPush = regCount;
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nextRegNum = val[elementIndex].RegNum + val[elementIndex].RegCount;
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lastElementIndex = elementIndex;
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}
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else
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{
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build->Emit(OP_MOVEF, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 1, yval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 2, zval.RegNum);
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regsToPush += regCount;
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nextRegNum = val[elementIndex].RegNum + val[elementIndex].RegCount;
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}
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xval.Free(build);
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yval.Free(build);
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zval.Free(build);
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return out;
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}
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// Emit move instructions on the last register
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if (regsToPush > 0)
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{
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emitRegMove(regsToPush, reg, lastElementIndex);
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}
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}
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else
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for (int i = 0; i < vectorElements; ++i)
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{
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assert(xyzw[3] != nullptr);
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ExpEmit tempxval = xyzw[0]->Emit(build);
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ExpEmit tempyval = xyzw[1]->Emit(build);
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ExpEmit tempzval = xyzw[2]->Emit(build);
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ExpEmit tempwval = xyzw[3]->Emit(build);
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ExpEmit xval = EmitKonst(build, tempxval);
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ExpEmit yval = EmitKonst(build, tempyval);
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ExpEmit zval = EmitKonst(build, tempzval);
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ExpEmit wval = EmitKonst(build, tempwval);
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assert(xval.RegType == REGT_FLOAT && yval.RegType == REGT_FLOAT && zval.RegType == REGT_FLOAT && wval.RegType == REGT_FLOAT);
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if (yval.RegNum == xval.RegNum + 1 && zval.RegNum == xval.RegNum + 2)
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{
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// The results are already in three continuous registers so just return them as-is.
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xval.RegCount += 3;
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return xval;
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}
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else
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{
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// The values are not in continuous registers so they need to be copied together now.
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ExpEmit out(build, REGT_FLOAT, 4);
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//Try to optimize a bit...
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if (yval.RegNum == xval.RegNum + 1)
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{
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build->Emit(OP_MOVEV2, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 2, zval.RegNum);
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}
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else if (zval.RegNum == yval.RegNum + 1)
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{
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build->Emit(OP_MOVEF, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEV2, out.RegNum+1, yval.RegNum);
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}
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else
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{
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build->Emit(OP_MOVEF, out.RegNum, xval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 1, yval.RegNum);
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build->Emit(OP_MOVEF, out.RegNum + 2, zval.RegNum);
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}
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xval.Free(build);
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yval.Free(build);
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zval.Free(build);
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return out;
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}
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val[i].Free(build);
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val[i].~ExpEmit();
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}
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return out;
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}
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//==========================================================================
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@ -3196,11 +3172,11 @@ ExpEmit FxMulDiv::Emit(VMFunctionBuilder *build)
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int op;
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if (op2.Konst)
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{
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op = Operator == '*' ? (IsVector2() ? OP_MULVF2_RK : OP_MULVF3_RK) : (IsVector2() ? OP_DIVVF2_RK : OP_DIVVF3_RK);
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op = Operator == '*' ? (IsVector2() ? OP_MULVF2_RK : IsVector3() ? OP_MULVF3_RK : OP_MULVF4_RK) : (IsVector2() ? OP_DIVVF2_RK : IsVector3() ? OP_DIVVF3_RK : OP_DIVVF4_RK);
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}
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else
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{
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op = Operator == '*' ? (IsVector2() ? OP_MULVF2_RR : OP_MULVF3_RR) : (IsVector2() ? OP_DIVVF2_RR : OP_DIVVF3_RR);
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op = Operator == '*' ? (IsVector2() ? OP_MULVF2_RR : IsVector3() ? OP_MULVF3_RR : OP_MULVF4_RR) : (IsVector2() ? OP_DIVVF2_RR : IsVector3() ? OP_DIVVF3_RR : OP_DIVVF4_RR);
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}
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op1.Free(build);
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op2.Free(build);
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@ -3903,7 +3879,7 @@ ExpEmit FxCompareEq::EmitCommon(VMFunctionBuilder *build, bool forcompare, bool
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std::swap(op1, op2);
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}
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assert(!op1.Konst);
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assert(op1.RegCount >= 1 && op1.RegCount <= 3);
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assert(op1.RegCount >= 1 && op1.RegCount <= 4);
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ExpEmit to(build, REGT_INT);
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@ -9222,15 +9198,19 @@ ExpEmit FxVectorBuiltin::Emit(VMFunctionBuilder *build)
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{
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ExpEmit to(build, ValueType->GetRegType(), ValueType->GetRegCount());
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ExpEmit op = Self->Emit(build);
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const int vecSize = (Self->ValueType == TypeVector2 || Self->ValueType == TypeFVector2) ? 2
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: (Self->ValueType == TypeVector3 || Self->ValueType == TypeFVector3) ? 3 : 4;
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if (Function == NAME_Length)
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{
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build->Emit(Self->ValueType == TypeVector2 || Self->ValueType == TypeFVector2 ? OP_LENV2 : Self->ValueType == TypeFVector3 ? OP_LENV3 : OP_LENV4, to.RegNum, op.RegNum);
|
||||
build->Emit(vecSize == 2 ? OP_LENV2 : vecSize == 3 ? OP_LENV3 : OP_LENV4, to.RegNum, op.RegNum);
|
||||
}
|
||||
else
|
||||
{
|
||||
ExpEmit len(build, REGT_FLOAT);
|
||||
build->Emit(Self->ValueType == TypeVector2 || Self->ValueType == TypeFVector2 ? OP_LENV2 : Self->ValueType == TypeFVector3 ? OP_LENV3 : OP_LENV4, to.RegNum, op.RegNum);
|
||||
build->Emit(Self->ValueType == TypeVector2 || Self->ValueType == TypeFVector2 ? OP_DIVVF2_RR : Self->ValueType == TypeFVector3 ? OP_DIVVF3_RR : OP_DIVVF4_RR, to.RegNum, op.RegNum, len.RegNum);
|
||||
build->Emit(vecSize == 2 ? OP_LENV2 : vecSize == 3 ? OP_LENV3 : OP_LENV4, len.RegNum, op.RegNum);
|
||||
build->Emit(vecSize == 2 ? OP_DIVVF2_RR : vecSize == 3 ? OP_DIVVF3_RR : OP_DIVVF4_RR, to.RegNum, op.RegNum, len.RegNum);
|
||||
len.Free(build);
|
||||
}
|
||||
op.Free(build);
|
||||
|
|
@ -10894,11 +10874,12 @@ FxLocalVariableDeclaration::FxLocalVariableDeclaration(PType *type, FName name,
|
|||
// Local FVector isn't different from Vector
|
||||
if (type == TypeFVector2) type = TypeVector2;
|
||||
else if (type == TypeFVector3) type = TypeVector3;
|
||||
else if (type == TypeFVector4) type = TypeVector4;
|
||||
|
||||
ValueType = type;
|
||||
VarFlags = varflags;
|
||||
Name = name;
|
||||
RegCount = type == TypeVector2 ? 2 : type == TypeVector3 ? 3 : 1;
|
||||
RegCount = type->RegCount;
|
||||
Init = initval;
|
||||
clearExpr = nullptr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -336,7 +336,7 @@ public:
|
|||
bool IsFloat() const { return ValueType->isFloat(); }
|
||||
bool IsInteger() const { return ValueType->isNumeric() && ValueType->isIntCompatible(); }
|
||||
bool IsPointer() const { return ValueType->isPointer(); }
|
||||
bool IsVector() const { return ValueType == TypeVector2 || ValueType == TypeVector3 || ValueType == TypeFVector2 || ValueType == TypeFVector3; };
|
||||
bool IsVector() const { return IsVector2() || IsVector3() || IsVector4(); };
|
||||
bool IsVector2() const { return ValueType == TypeVector2 || ValueType == TypeFVector2; };
|
||||
bool IsVector3() const { return ValueType == TypeVector3 || ValueType == TypeFVector3; };
|
||||
bool IsVector4() const { return ValueType == TypeVector4 || ValueType == TypeFVector4; };
|
||||
|
|
@ -551,7 +551,9 @@ public:
|
|||
|
||||
class FxVectorValue : public FxExpression
|
||||
{
|
||||
FxExpression *xyzw[4];
|
||||
constexpr static int maxVectorDimensions = 4;
|
||||
|
||||
FxExpression *xyzw[maxVectorDimensions];
|
||||
bool isConst; // gets set to true if all element are const (used by function defaults parser)
|
||||
|
||||
public:
|
||||
|
|
@ -563,8 +565,9 @@ public:
|
|||
FxExpression *Resolve(FCompileContext&);
|
||||
bool isConstVector(int dim)
|
||||
{
|
||||
if (!isConst) return false;
|
||||
return dim == 2 ? xyzw[2] == nullptr : xyzw[2] != nullptr;
|
||||
if (!isConst)
|
||||
return false;
|
||||
return dim >= 0 && dim <= maxVectorDimensions && xyzw[dim - 1] && (dim == maxVectorDimensions || !xyzw[dim]);
|
||||
}
|
||||
|
||||
ExpEmit Emit(VMFunctionBuilder *build);
|
||||
|
|
|
|||
|
|
@ -637,6 +637,7 @@ size_t VMFunctionBuilder::Emit(int opcode, int opa, VM_SHALF opbc)
|
|||
int chg;
|
||||
if (opa & REGT_MULTIREG2) chg = 2;
|
||||
else if (opa & REGT_MULTIREG3) chg = 3;
|
||||
else if (opa & REGT_MULTIREG4) chg = 4;
|
||||
else chg = 1;
|
||||
ParamChange(chg);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -359,12 +359,13 @@ void PType::StaticInit()
|
|||
TypeVector4->AddField(NAME_W, TypeFloat64);
|
||||
// allow accessing xyz as a vector3. This is not supposed to be serialized so it's marked transient
|
||||
TypeVector4->Symbols.AddSymbol(Create<PField>(NAME_XYZ, TypeVector3, VARF_Transient, 0));
|
||||
TypeVector4->Symbols.AddSymbol(Create<PField>(NAME_XY, TypeVector2, VARF_Transient, 0));
|
||||
TypeTable.AddType(TypeVector4, NAME_Struct);
|
||||
TypeVector4->loadOp = OP_LV4;
|
||||
TypeVector4->storeOp = OP_SV4;
|
||||
TypeVector4->moveOp = OP_MOVEV4;
|
||||
TypeVector4->RegType = REGT_FLOAT;
|
||||
TypeVector4->RegCount = 3;
|
||||
TypeVector4->RegCount = 4;
|
||||
TypeVector4->isOrdered = true;
|
||||
|
||||
|
||||
|
|
@ -398,8 +399,9 @@ void PType::StaticInit()
|
|||
TypeFVector4->AddField(NAME_Y, TypeFloat32);
|
||||
TypeFVector4->AddField(NAME_Z, TypeFloat32);
|
||||
TypeFVector4->AddField(NAME_W, TypeFloat32);
|
||||
// allow accessing xy as a vector2
|
||||
// allow accessing xyz as a vector3
|
||||
TypeFVector4->Symbols.AddSymbol(Create<PField>(NAME_XYZ, TypeFVector3, VARF_Transient, 0));
|
||||
TypeFVector4->Symbols.AddSymbol(Create<PField>(NAME_XY, TypeFVector2, VARF_Transient, 0));
|
||||
TypeTable.AddType(TypeFVector4, NAME_Struct);
|
||||
TypeFVector4->loadOp = OP_LFV4;
|
||||
TypeFVector4->storeOp = OP_SFV4;
|
||||
|
|
|
|||
|
|
@ -639,6 +639,8 @@ static int print_reg(FILE *out, int col, int arg, int mode, int immshift, const
|
|||
return col+printf_wrapper(out, "v%d.2", regnum);
|
||||
case REGT_FLOAT | REGT_MULTIREG3:
|
||||
return col+printf_wrapper(out, "v%d.3", regnum);
|
||||
case REGT_FLOAT | REGT_MULTIREG4:
|
||||
return col+printf_wrapper(out, "v%d.4", regnum);
|
||||
case REGT_INT | REGT_KONST:
|
||||
return col+print_reg(out, 0, regnum, MODE_KI, 0, func);
|
||||
case REGT_FLOAT | REGT_KONST:
|
||||
|
|
|
|||
|
|
@ -861,6 +861,7 @@ type_name1(X) ::= DOUBLE(T). { X.Int = ZCC_Float64; X.SourceLoc = T.SourceLoc
|
|||
//type_name1(X) ::= STRING(T). { X.Int = ZCC_String; X.SourceLoc = T.SourceLoc; } // [ZZ] it's handled elsewhere. this particular line only causes troubles in the form of String.Format being invalid.
|
||||
type_name1(X) ::= VECTOR2(T). { X.Int = ZCC_Vector2; X.SourceLoc = T.SourceLoc; }
|
||||
type_name1(X) ::= VECTOR3(T). { X.Int = ZCC_Vector3; X.SourceLoc = T.SourceLoc; }
|
||||
type_name1(X) ::= VECTOR4(T). { X.Int = ZCC_Vector4; X.SourceLoc = T.SourceLoc; }
|
||||
type_name1(X) ::= NAME(T). { X.Int = ZCC_Name; X.SourceLoc = T.SourceLoc; }
|
||||
type_name1(X) ::= SOUND(T). { X.Int = ZCC_Sound; X.SourceLoc = T.SourceLoc; }
|
||||
type_name1(X) ::= STATE(T). { X.Int = ZCC_State; X.SourceLoc = T.SourceLoc; }
|
||||
|
|
@ -931,7 +932,7 @@ type_name(X) ::= DOT dottable_id(A).
|
|||
/* Type names can also be used as identifiers in contexts where type names
|
||||
* are not normally allowed. */
|
||||
%fallback IDENTIFIER
|
||||
SBYTE BYTE SHORT USHORT INT UINT BOOL FLOAT DOUBLE STRING VECTOR2 VECTOR3 NAME MAP ARRAY VOID STATE COLOR SOUND UINT8 INT8 UINT16 INT16 PROPERTY.
|
||||
SBYTE BYTE SHORT USHORT INT UINT BOOL FLOAT DOUBLE STRING VECTOR2 VECTOR3 VECTOR4 NAME MAP ARRAY VOID STATE COLOR SOUND UINT8 INT8 UINT16 INT16 PROPERTY.
|
||||
|
||||
/* Aggregate types */
|
||||
%type aggregate_type {ZCC_Type *}
|
||||
|
|
@ -1303,6 +1304,17 @@ primary(X) ::= SUPER(T).
|
|||
X = expr;
|
||||
}
|
||||
primary(X) ::= constant(A). { X = A; /*X-overwrites-A*/ }
|
||||
primary(XX) ::= LPAREN expr(A) COMMA expr(B) COMMA expr(C) COMMA expr(D) RPAREN. [DOT]
|
||||
{
|
||||
NEW_AST_NODE(VectorValue, expr, A);
|
||||
expr->Operation = PEX_Vector;
|
||||
expr->Type = TypeVector4;
|
||||
expr->X = A;
|
||||
expr->Y = B;
|
||||
expr->Z = C;
|
||||
expr->W = D;
|
||||
XX = expr;
|
||||
}
|
||||
primary(XX) ::= LPAREN expr(A) COMMA expr(B) COMMA expr(C) RPAREN. [DOT]
|
||||
{
|
||||
NEW_AST_NODE(VectorValue, expr, A);
|
||||
|
|
@ -1311,6 +1323,7 @@ primary(XX) ::= LPAREN expr(A) COMMA expr(B) COMMA expr(C) RPAREN. [DOT]
|
|||
expr->X = A;
|
||||
expr->Y = B;
|
||||
expr->Z = C;
|
||||
expr->W = nullptr;
|
||||
XX = expr;
|
||||
}
|
||||
primary(XX) ::= LPAREN expr(A) COMMA expr(B) RPAREN. [DOT]
|
||||
|
|
@ -1321,6 +1334,7 @@ primary(XX) ::= LPAREN expr(A) COMMA expr(B) RPAREN. [DOT]
|
|||
expr->X = A;
|
||||
expr->Y = B;
|
||||
expr->Z = nullptr;
|
||||
expr->W = nullptr;
|
||||
XX = expr;
|
||||
}
|
||||
primary(X) ::= LPAREN expr(A) RPAREN.
|
||||
|
|
|
|||
|
|
@ -2353,7 +2353,7 @@ void ZCCCompiler::CompileFunction(ZCC_StructWork *c, ZCC_FuncDeclarator *f, bool
|
|||
{
|
||||
auto type = DetermineType(c->Type(), p, f->Name, p->Type, false, false);
|
||||
int flags = 0;
|
||||
if ((type->isStruct() && type != TypeVector2 && type != TypeVector3) || type->isDynArray())
|
||||
if ((type->isStruct() && type != TypeVector2 && type != TypeVector3 && type != TypeVector4) || type->isDynArray())
|
||||
{
|
||||
// Structs are being passed by pointer, but unless marked 'out' that pointer must be readonly.
|
||||
type = NewPointer(type /*, !(p->Flags & ZCC_Out)*/);
|
||||
|
|
|
|||
|
|
@ -1297,7 +1297,8 @@ ZCC_TreeNode *TreeNodeDeepCopy_Internal(ZCC_AST *ast, ZCC_TreeNode *orig, bool c
|
|||
// ZCC_VectorValue
|
||||
copy->X = static_cast<ZCC_Expression *>(TreeNodeDeepCopy_Internal(ast, origCasted->X, true, copiedNodesList));
|
||||
copy->Y = static_cast<ZCC_Expression *>(TreeNodeDeepCopy_Internal(ast, origCasted->Y, true, copiedNodesList));
|
||||
copy->Z = static_cast<ZCC_Expression *>(TreeNodeDeepCopy_Internal(ast, origCasted->Z, true, copiedNodesList));
|
||||
copy->Z = static_cast<ZCC_Expression*>(TreeNodeDeepCopy_Internal(ast, origCasted->Z, true, copiedNodesList));
|
||||
copy->W = static_cast<ZCC_Expression*>(TreeNodeDeepCopy_Internal(ast, origCasted->W, true, copiedNodesList));
|
||||
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -182,6 +182,13 @@ int JitCompiler::StoreCallParams()
|
|||
}
|
||||
numparams += 2;
|
||||
break;
|
||||
case REGT_FLOAT | REGT_MULTIREG4:
|
||||
for (int j = 0; j < 4; j++)
|
||||
{
|
||||
cc.movsd(x86::qword_ptr(vmframe, offsetParams + (slot + j) * sizeof(VMValue) + myoffsetof(VMValue, f)), regF[bc + j]);
|
||||
}
|
||||
numparams += 3;
|
||||
break;
|
||||
case REGT_FLOAT | REGT_ADDROF:
|
||||
cc.lea(stackPtr, x86::ptr(vmframe, offsetF + (int)(bc * sizeof(double))));
|
||||
// When passing the address to a float we don't know if the receiving function will treat it as float, vec2 or vec3.
|
||||
|
|
@ -256,6 +263,12 @@ void JitCompiler::LoadCallResult(int type, int regnum, bool addrof)
|
|||
cc.movsd(regF[regnum + 1], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 1) * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 2], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 2) * sizeof(double)));
|
||||
}
|
||||
else if (type & REGT_MULTIREG4)
|
||||
{
|
||||
cc.movsd(regF[regnum + 1], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 1) * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 2], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 2) * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 3], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 3) * sizeof(double)));
|
||||
}
|
||||
break;
|
||||
case REGT_STRING:
|
||||
// We don't have to do anything in this case. String values are never moved to virtual registers.
|
||||
|
|
@ -408,6 +421,11 @@ void JitCompiler::EmitNativeCall(VMNativeFunction *target)
|
|||
call->setArg(slot + j, regF[bc + j]);
|
||||
numparams += 2;
|
||||
break;
|
||||
case REGT_FLOAT | REGT_MULTIREG4:
|
||||
for (int j = 0; j < 4; j++)
|
||||
call->setArg(slot + j, regF[bc + j]);
|
||||
numparams += 3;
|
||||
break;
|
||||
case REGT_FLOAT | REGT_KONST:
|
||||
tmp = newTempIntPtr();
|
||||
tmp2 = newTempXmmSd();
|
||||
|
|
@ -550,6 +568,12 @@ void JitCompiler::EmitNativeCall(VMNativeFunction *target)
|
|||
cc.movsd(regF[regnum + 1], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 1) * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 2], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 2) * sizeof(double)));
|
||||
break;
|
||||
case REGT_FLOAT | REGT_MULTIREG4:
|
||||
cc.movsd(regF[regnum], asmjit::x86::qword_ptr(vmframe, offsetF + regnum * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 1], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 1) * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 2], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 2) * sizeof(double)));
|
||||
cc.movsd(regF[regnum + 3], asmjit::x86::qword_ptr(vmframe, offsetF + (regnum + 3) * sizeof(double)));
|
||||
break;
|
||||
case REGT_STRING:
|
||||
// We don't have to do anything in this case. String values are never moved to virtual registers.
|
||||
break;
|
||||
|
|
@ -624,6 +648,13 @@ asmjit::FuncSignature JitCompiler::CreateFuncSignature()
|
|||
args.Push(TypeIdOf<double>::kTypeId);
|
||||
key += "fff";
|
||||
break;
|
||||
case REGT_FLOAT | REGT_MULTIREG4:
|
||||
args.Push(TypeIdOf<double>::kTypeId);
|
||||
args.Push(TypeIdOf<double>::kTypeId);
|
||||
args.Push(TypeIdOf<double>::kTypeId);
|
||||
args.Push(TypeIdOf<double>::kTypeId);
|
||||
key += "ffff";
|
||||
break;
|
||||
|
||||
default:
|
||||
I_Error("Unknown REGT value passed to EmitPARAM\n");
|
||||
|
|
|
|||
|
|
@ -110,7 +110,21 @@ void JitCompiler::EmitRET()
|
|||
if (regtype & REGT_KONST)
|
||||
{
|
||||
auto tmp = newTempInt64();
|
||||
if (regtype & REGT_MULTIREG3)
|
||||
if (regtype & REGT_MULTIREG4)
|
||||
{
|
||||
cc.mov(tmp, (((int64_t*)konstf)[regnum]));
|
||||
cc.mov(x86::qword_ptr(location), tmp);
|
||||
|
||||
cc.mov(tmp, (((int64_t*)konstf)[regnum + 1]));
|
||||
cc.mov(x86::qword_ptr(location, 8), tmp);
|
||||
|
||||
cc.mov(tmp, (((int64_t*)konstf)[regnum + 2]));
|
||||
cc.mov(x86::qword_ptr(location, 16), tmp);
|
||||
|
||||
cc.mov(tmp, (((int64_t*)konstf)[regnum + 3]));
|
||||
cc.mov(x86::qword_ptr(location, 24), tmp);
|
||||
}
|
||||
else if (regtype & REGT_MULTIREG3)
|
||||
{
|
||||
cc.mov(tmp, (((int64_t *)konstf)[regnum]));
|
||||
cc.mov(x86::qword_ptr(location), tmp);
|
||||
|
|
@ -137,7 +151,14 @@ void JitCompiler::EmitRET()
|
|||
}
|
||||
else
|
||||
{
|
||||
if (regtype & REGT_MULTIREG3)
|
||||
if (regtype & REGT_MULTIREG4)
|
||||
{
|
||||
cc.movsd(x86::qword_ptr(location), regF[regnum]);
|
||||
cc.movsd(x86::qword_ptr(location, 8), regF[regnum + 1]);
|
||||
cc.movsd(x86::qword_ptr(location, 16), regF[regnum + 2]);
|
||||
cc.movsd(x86::qword_ptr(location, 24), regF[regnum + 3]);
|
||||
}
|
||||
else if (regtype & REGT_MULTIREG3)
|
||||
{
|
||||
cc.movsd(x86::qword_ptr(location), regF[regnum]);
|
||||
cc.movsd(x86::qword_ptr(location, 8), regF[regnum + 1]);
|
||||
|
|
|
|||
|
|
@ -333,7 +333,7 @@ void JitCompiler::EmitLV4()
|
|||
cc.movsd(regF[A], asmjit::x86::qword_ptr(tmp));
|
||||
cc.movsd(regF[A + 1], asmjit::x86::qword_ptr(tmp, 8));
|
||||
cc.movsd(regF[A + 2], asmjit::x86::qword_ptr(tmp, 16));
|
||||
cc.movsd(regF[A + 3], asmjit::x86::qword_ptr(tmp, 32));
|
||||
cc.movsd(regF[A + 3], asmjit::x86::qword_ptr(tmp, 24));
|
||||
}
|
||||
|
||||
void JitCompiler::EmitLV4_R()
|
||||
|
|
@ -344,7 +344,7 @@ void JitCompiler::EmitLV4_R()
|
|||
cc.movsd(regF[A], asmjit::x86::qword_ptr(tmp));
|
||||
cc.movsd(regF[A + 1], asmjit::x86::qword_ptr(tmp, 8));
|
||||
cc.movsd(regF[A + 2], asmjit::x86::qword_ptr(tmp, 16));
|
||||
cc.movsd(regF[A + 3], asmjit::x86::qword_ptr(tmp, 32));
|
||||
cc.movsd(regF[A + 3], asmjit::x86::qword_ptr(tmp, 24));
|
||||
}
|
||||
|
||||
void JitCompiler::EmitLFV2()
|
||||
|
|
@ -403,7 +403,7 @@ void JitCompiler::EmitLFV4()
|
|||
cc.movss(regF[A], asmjit::x86::qword_ptr(tmp));
|
||||
cc.movss(regF[A + 1], asmjit::x86::qword_ptr(tmp, 4));
|
||||
cc.movss(regF[A + 2], asmjit::x86::qword_ptr(tmp, 8));
|
||||
cc.movss(regF[A + 3], asmjit::x86::qword_ptr(tmp, 16));
|
||||
cc.movss(regF[A + 3], asmjit::x86::qword_ptr(tmp, 12));
|
||||
cc.cvtss2sd(regF[A], regF[A]);
|
||||
cc.cvtss2sd(regF[A + 1], regF[A + 1]);
|
||||
cc.cvtss2sd(regF[A + 2], regF[A + 2]);
|
||||
|
|
@ -418,7 +418,7 @@ void JitCompiler::EmitLFV4_R()
|
|||
cc.movss(regF[A], asmjit::x86::qword_ptr(tmp));
|
||||
cc.movss(regF[A + 1], asmjit::x86::qword_ptr(tmp, 4));
|
||||
cc.movss(regF[A + 2], asmjit::x86::qword_ptr(tmp, 8));
|
||||
cc.movss(regF[A + 3], asmjit::x86::qword_ptr(tmp, 16));
|
||||
cc.movss(regF[A + 3], asmjit::x86::qword_ptr(tmp, 12));
|
||||
cc.cvtss2sd(regF[A], regF[A]);
|
||||
cc.cvtss2sd(regF[A + 1], regF[A + 1]);
|
||||
cc.cvtss2sd(regF[A + 2], regF[A + 2]);
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@ void JitCompiler::EmitSV4()
|
|||
cc.movsd(asmjit::x86::qword_ptr(tmp), regF[B]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 8), regF[B + 1]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 16), regF[B + 2]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 32), regF[B + 3]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 24), regF[B + 3]);
|
||||
}
|
||||
|
||||
void JitCompiler::EmitSV4_R()
|
||||
|
|
@ -182,7 +182,7 @@ void JitCompiler::EmitSV4_R()
|
|||
cc.movsd(asmjit::x86::qword_ptr(tmp), regF[B]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 8), regF[B + 1]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 16), regF[B + 2]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 32), regF[B + 3]);
|
||||
cc.movsd(asmjit::x86::qword_ptr(tmp, 24), regF[B + 3]);
|
||||
}
|
||||
|
||||
void JitCompiler::EmitSFV2()
|
||||
|
|
@ -257,7 +257,7 @@ void JitCompiler::EmitSFV4()
|
|||
cc.cvtsd2ss(tmpF, regF[B + 2]);
|
||||
cc.movss(asmjit::x86::qword_ptr(tmp, 8), tmpF);
|
||||
cc.cvtsd2ss(tmpF, regF[B + 3]);
|
||||
cc.movss(asmjit::x86::qword_ptr(tmp, 16), tmpF);
|
||||
cc.movss(asmjit::x86::qword_ptr(tmp, 12), tmpF);
|
||||
}
|
||||
|
||||
void JitCompiler::EmitSFV4_R()
|
||||
|
|
@ -274,7 +274,7 @@ void JitCompiler::EmitSFV4_R()
|
|||
cc.cvtsd2ss(tmpF, regF[B + 2]);
|
||||
cc.movss(asmjit::x86::qword_ptr(tmp, 8), tmpF);
|
||||
cc.cvtsd2ss(tmpF, regF[B + 3]);
|
||||
cc.movss(asmjit::x86::qword_ptr(tmp, 16), tmpF);
|
||||
cc.movss(asmjit::x86::qword_ptr(tmp, 12), tmpF);
|
||||
}
|
||||
|
||||
void JitCompiler::EmitSBIT()
|
||||
|
|
|
|||
|
|
@ -80,8 +80,9 @@ enum
|
|||
REGT_KONST = 4,
|
||||
REGT_MULTIREG2 = 8,
|
||||
REGT_MULTIREG3 = 16, // (e.g. a vector)
|
||||
REGT_MULTIREG = 24,
|
||||
REGT_MULTIREG = 8 | 16 | 64,
|
||||
REGT_ADDROF = 32, // used with PARAM: pass address of this register
|
||||
REGT_MULTIREG4 = 64,
|
||||
|
||||
REGT_NIL = 128 // parameter was omitted
|
||||
};
|
||||
|
|
@ -130,6 +131,22 @@ struct VMReturn
|
|||
assert(RegType == REGT_FLOAT);
|
||||
*(double *)Location = val;
|
||||
}
|
||||
void SetVector4(const double val[4])
|
||||
{
|
||||
assert(RegType == (REGT_FLOAT|REGT_MULTIREG4));
|
||||
((double *)Location)[0] = val[0];
|
||||
((double *)Location)[1] = val[1];
|
||||
((double *)Location)[2] = val[2];
|
||||
((double *)Location)[3] = val[3];
|
||||
}
|
||||
void SetVector4(const DVector4 &val)
|
||||
{
|
||||
assert(RegType == (REGT_FLOAT | REGT_MULTIREG4));
|
||||
((double *)Location)[0] = val[0];
|
||||
((double *)Location)[1] = val[1];
|
||||
((double *)Location)[2] = val[2];
|
||||
((double *)Location)[3] = val[3];
|
||||
}
|
||||
void SetVector(const double val[3])
|
||||
{
|
||||
assert(RegType == (REGT_FLOAT|REGT_MULTIREG3));
|
||||
|
|
|
|||
|
|
@ -512,6 +512,28 @@ static int ExecScriptFunc(VMFrameStack *stack, VMReturn *ret, int numret)
|
|||
v[2] = reg.f[B+2];
|
||||
}
|
||||
NEXTOP;
|
||||
OP(SV4):
|
||||
ASSERTA(a); ASSERTF(B+3); ASSERTKD(C);
|
||||
GETADDR(PA,KC,X_WRITE_NIL);
|
||||
{
|
||||
auto v = (double *)ptr;
|
||||
v[0] = reg.f[B];
|
||||
v[1] = reg.f[B+1];
|
||||
v[2] = reg.f[B+2];
|
||||
v[3] = reg.f[B+3];
|
||||
}
|
||||
NEXTOP;
|
||||
OP(SV4_R):
|
||||
ASSERTA(a); ASSERTF(B+3); ASSERTD(C);
|
||||
GETADDR(PA,RC,X_WRITE_NIL);
|
||||
{
|
||||
auto v = (double *)ptr;
|
||||
v[0] = reg.f[B];
|
||||
v[1] = reg.f[B+1];
|
||||
v[2] = reg.f[B+2];
|
||||
v[3] = reg.f[B+3];
|
||||
}
|
||||
NEXTOP;
|
||||
OP(SFV2):
|
||||
ASSERTA(a); ASSERTF(B+1); ASSERTKD(C);
|
||||
GETADDR(PA,KC,X_WRITE_NIL);
|
||||
|
|
@ -550,6 +572,28 @@ static int ExecScriptFunc(VMFrameStack *stack, VMReturn *ret, int numret)
|
|||
v[2] = (float)reg.f[B+2];
|
||||
}
|
||||
NEXTOP;
|
||||
OP(SFV4):
|
||||
ASSERTA(a); ASSERTF(B+3); ASSERTKD(C);
|
||||
GETADDR(PA,KC,X_WRITE_NIL);
|
||||
{
|
||||
auto v = (float *)ptr;
|
||||
v[0] = (float)reg.f[B];
|
||||
v[1] = (float)reg.f[B+1];
|
||||
v[2] = (float)reg.f[B+2];
|
||||
v[3] = (float)reg.f[B+3];
|
||||
}
|
||||
NEXTOP;
|
||||
OP(SFV4_R):
|
||||
ASSERTA(a); ASSERTF(B+3); ASSERTD(C);
|
||||
GETADDR(PA,RC,X_WRITE_NIL);
|
||||
{
|
||||
auto v = (float *)ptr;
|
||||
v[0] = (float)reg.f[B];
|
||||
v[1] = (float)reg.f[B+1];
|
||||
v[2] = (float)reg.f[B+2];
|
||||
v[3] = (float)reg.f[B+3];
|
||||
}
|
||||
NEXTOP;
|
||||
OP(SBIT):
|
||||
ASSERTA(a); ASSERTD(B);
|
||||
GETADDR(PA,0,X_WRITE_NIL);
|
||||
|
|
@ -767,6 +811,15 @@ static int ExecScriptFunc(VMFrameStack *stack, VMReturn *ret, int numret)
|
|||
::new(param + 2) VMValue(reg.f[b + 2]);
|
||||
f->NumParam += 2;
|
||||
break;
|
||||
case REGT_FLOAT | REGT_MULTIREG4:
|
||||
assert(b < f->NumRegF - 3);
|
||||
assert(f->NumParam < sfunc->MaxParam - 2);
|
||||
::new(param) VMValue(reg.f[b]);
|
||||
::new(param + 1) VMValue(reg.f[b + 1]);
|
||||
::new(param + 2) VMValue(reg.f[b + 2]);
|
||||
::new(param + 3) VMValue(reg.f[b + 3]);
|
||||
f->NumParam += 3;
|
||||
break;
|
||||
case REGT_FLOAT | REGT_ADDROF:
|
||||
assert(b < f->NumRegF);
|
||||
::new(param) VMValue(®.f[b]);
|
||||
|
|
@ -2173,7 +2226,11 @@ static void SetReturn(const VMRegisters ®, VMFrame *frame, VMReturn *ret, VM_
|
|||
assert(regnum < frame->NumRegF);
|
||||
src = ®.f[regnum];
|
||||
}
|
||||
if (regtype & REGT_MULTIREG3)
|
||||
if (regtype & REGT_MULTIREG4)
|
||||
{
|
||||
ret->SetVector4((double*)src);
|
||||
}
|
||||
else if (regtype & REGT_MULTIREG3)
|
||||
{
|
||||
ret->SetVector((double *)src);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,8 +85,8 @@ xx(SV2, sv2, RPRVKI, SV2_R, 4, REGT_INT) // store vector2
|
|||
xx(SV2_R, sv2, RPRVRI, NOP, 0, 0)
|
||||
xx(SV3, sv3, RPRVKI, SV3_R, 4, REGT_INT) // store vector3
|
||||
xx(SV3_R, sv3, RPRVRI, NOP, 0, 0)
|
||||
xx(SV4, sv3, RPRVKI, SV4_R, 4, REGT_INT) // store vector4
|
||||
xx(SV4_R, sv3, RPRVRI, NOP, 0, 0)
|
||||
xx(SV4, sv4, RPRVKI, SV4_R, 4, REGT_INT) // store vector4
|
||||
xx(SV4_R, sv4, RPRVRI, NOP, 0, 0)
|
||||
xx(SFV2, sfv2, RPRVKI, SFV2_R, 4, REGT_INT) // store fvector2
|
||||
xx(SFV2_R, sfv2, RPRVRI, NOP, 0, 0)
|
||||
xx(SFV3, sfv3, RPRVKI, SFV3_R, 4, REGT_INT) // store fvector3
|
||||
|
|
@ -265,7 +265,7 @@ xx(LENV3, lenv3, RFRV, NOP, 0, 0) // fA = vB.Length
|
|||
xx(EQV3_R, beqv3, CVRR, NOP, 0, 0) // if ((vB == vkC) != A) then pc++ (inexact if A & 33)
|
||||
xx(EQV3_K, beqv3, CVRK, NOP, 0, 0) // this will never be used.
|
||||
|
||||
// Vector math (4D/Quaternion)
|
||||
// Vector math (4D)
|
||||
xx(NEGV4, negv4, RVRV, NOP, 0, 0) // vA = -vB
|
||||
xx(ADDV4_RR, addv4, RVRVRV, NOP, 0, 0) // vA = vB + vkC
|
||||
xx(SUBV4_RR, subv4, RVRVRV, NOP, 0, 0) // vA = vkB - vkC
|
||||
|
|
|
|||
Loading…
Reference in a new issue