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https://github.com/DrBeef/Raze.git
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Add WIP x86_64 assembly texture mapping routines.
- Currently: only tvlineasm1 and tvlineasm2, but incomplete (no reverse translucency, nonpow2 textures will crash) - For System V AMD64 calling conventions; requires YASM git-svn-id: https://svn.eduke32.com/eduke32@4066 1a8010ca-5511-0410-912e-c29ae57300e0
This commit is contained in:
helixhorned
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commit
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5 changed files with 272 additions and 7 deletions
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@ -146,6 +146,9 @@ USE_LIBVPX ?= 1
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NETCODE ?= 1
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LUNATIC ?= 0
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# EXPERIMENTAL, unfinished x86_64 assembly routines. DO NOT ENABLE.
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USE_ASM64 ?= 0
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ifeq (0,$(USE_OPENGL))
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POLYMER = 0
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USE_LIBVPX = 0
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@ -52,6 +52,9 @@ ifeq (0,$(NOASM))
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ENGINEOBJS+= $(OBJ)/a.$o
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else
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ENGINEOBJS+= $(OBJ)/a-c.$o
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ifneq (0,$(USE_ASM64))
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ENGINEOBJS+= $(OBJ)/a64.$o
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endif
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endif
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@ -288,6 +291,11 @@ $(OBJ)/%.$o: $(SRC)/%.nasm
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$(COMPILE_STATUS)
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if $(AS) $(OURASFLAGS) $< -o $@; then $(COMPILE_OK); else $(COMPILE_FAILED); fi
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# TODO: Makefile vars...
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$(OBJ)/%.$o: $(SRC)/%.yasm
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$(COMPILE_STATUS)
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if yasm -f elf64 $< -o $@; then $(COMPILE_OK); else $(COMPILE_FAILED); fi
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# Comment out the following rule to debug a-c.o
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$(OBJ)/a-c.$o: $(SRC)/a-c.c
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$(COMPILE_STATUS)
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@ -244,6 +244,9 @@ endif
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ifneq (0,$(NOASM))
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BUILDCOMMONFLAGS+= -DNOASM
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endif
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ifneq (0,$(USE_ASM64))
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BUILDCOMMONFLAGS+= -DUSE_ASM64
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endif
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ifneq (0,$(LINKED_GTK))
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BUILDCOMMONFLAGS+= -DLINKED_GTK
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endif
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@ -19,16 +19,33 @@ extern intptr_t asm1, asm2, asm3, asm4;
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extern int32_t fpuasm, globalx3, globaly3;
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extern void *reciptable;
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#ifdef USE_ASM64
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# define A64_ASSIGN(var, val) var=val
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#else
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# define A64_ASSIGN(var, val)
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#endif
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#ifdef USE_ASM64
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// variables for a64.yasm
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int32_t a64_bpl, a64_transmode, a64_glogy;
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intptr_t a64_paloffs;
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char *a64_gtrans;
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#endif
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static int32_t bpl, transmode = 0;
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static int32_t glogx, glogy, gbxinc, gbyinc, gpinc;
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static char *gbuf, *gpal, *ghlinepal, *gtrans;
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static char *gpal2;
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//Global variable functions
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void setvlinebpl(int32_t dabpl) { bpl = dabpl; }
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void fixtransluscence(intptr_t datransoff) { gtrans = (char *)datransoff; }
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void settransnormal(void) { transmode = 0; }
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void settransreverse(void) { transmode = 1; }
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void setvlinebpl(int32_t dabpl) { A64_ASSIGN(a64_bpl, dabpl); bpl = dabpl;}
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void fixtransluscence(intptr_t datransoff)
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{
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A64_ASSIGN(a64_gtrans, (char *)datransoff);
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gtrans = (char *)datransoff;
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}
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void settransnormal(void) { A64_ASSIGN(a64_transmode, 0); transmode = 0; }
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void settransreverse(void) { A64_ASSIGN(a64_transmode, 1); transmode = 1; }
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///// Ceiling/floor horizontal line functions /////
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@ -230,8 +247,18 @@ void mvlineasm4(int32_t cnt, char *p)
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Bmemcpy(vplce, vplc, sizeof(vplce));
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}
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#ifdef USE_ASM64
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# define GLOGY a64_glogy
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#else
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# define GLOGY glogy
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#endif
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void setuptvlineasm(int32_t neglogy) { glogy = neglogy; }
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void setuptvlineasm(int32_t neglogy)
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{
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GLOGY = neglogy;
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}
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#if !defined USE_ASM64
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// cnt+1 loop iterations!
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int32_t tvlineasm1(int32_t vinc, intptr_t paloffs, int32_t cnt, uint32_t vplc, intptr_t bufplc, intptr_t p)
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{
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@ -270,13 +297,17 @@ int32_t tvlineasm1(int32_t vinc, intptr_t paloffs, int32_t cnt, uint32_t vplc, i
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return vplc;
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}
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#endif
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void setuptvlineasm2(int32_t neglogy, intptr_t paloffs1, intptr_t paloffs2)
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{
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glogy = neglogy;
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GLOGY = neglogy;
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A64_ASSIGN(a64_paloffs, paloffs1);
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gpal = (char *)paloffs1;
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gpal2 = (char *)paloffs2;
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}
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#if !defined USE_ASM64
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// Pass: asm1=vinc2, asm2=pend
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// Return: asm1=vplc1, asm2=vplc2
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void tvlineasm2(uint32_t vplc2, int32_t vinc1, intptr_t bufplc1, intptr_t bufplc2, uint32_t vplc1, intptr_t p)
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@ -330,7 +361,7 @@ void tvlineasm2(uint32_t vplc2, int32_t vinc1, intptr_t bufplc1, intptr_t bufplc
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asm1 = vplc1;
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asm2 = vplc2;
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}
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#endif
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//Floor sprite horizontal line functions
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void msethlineshift(int32_t logx, int32_t logy) { glogx = logx; glogy = logy; }
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220
polymer/eduke32/build/src/a64.yasm
Normal file
220
polymer/eduke32/build/src/a64.yasm
Normal file
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@ -0,0 +1,220 @@
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;;; x86_64 assembly for basic texture mapping functions, based on a.nasm.
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;;; For use with System V AMD64 calling convention (rdi rsi rdx rcx r8 r9)
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;;; See the included license file "BUILDLIC.TXT" for license info.
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SECTION .text
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%ifdef UNDERSCORES
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%define asm1 _asm1
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%define asm2 _asm2
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%define a64_bpl _a64_bpl
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%define a64_transmode _a64_transmode
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%define a64_glogy _a64_glogy
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%define a64_gtrans _a64_gtrans
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%define a64_paloffs _a64_paloffs
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%define tvlineasm1 _tvlineasm1
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%define tvlineasm2 _tvlineasm2
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%endif
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;;; Imports
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EXTERN asm1 ; intptr_t
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EXTERN asm2 ; intptr_t
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EXTERN a64_bpl ; int32_t
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EXTERN a64_transmode ; int32_t
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EXTERN a64_glogy ; int32_t
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EXTERN a64_gtrans ; char *
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EXTERN a64_paloffs ; intptr_t
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;;; Exports
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GLOBAL tvlineasm1 ; Masked & transluscent 1-pixel wide vline
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GLOBAL tvlineasm2 ; Masked & transluscent 2-pixel wide vline
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;;; ========== MACROS ==========
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; Construct name referring to low doubleword of GPR, only for r8-r15.
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%define REGd(reg) reg %+ d
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; Construct name of whole GPR from word-sized register, only for ax-bp.
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%define rREG(regw) r %+ regw
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; Construct name of low doubleword of GPR from word-sized register, only for ax-bp.
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%define eREG(regw) e %+ regw
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;;; Multi-line macros for code shared between functions
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;; Prologue getters
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%macro PGET_rBpl 0
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push rBpl
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mov REGd(rBpl), dword [rel a64_bpl]
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%endmacro
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%macro PGET_rATransluc 0
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push rATransluc
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mov rATransluc, [rel a64_gtrans]
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%endmacro
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; Get right shift count 'glogy' into cl
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%macro GET_cl 0
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mov cl, byte [rel a64_glogy]
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%endmacro
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; Look up texel
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; <dest_reg_lobyte> := bufplc[vplc>>glogy]
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; High bytes are cleared to zero.
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%macro gettexel 3 ; <dest_reg_word> <bufplc_reg> <vlpc_reg>
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mov eREG(%1), %3
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shr eREG(%1), cl
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movzx eREG(%1), byte [%2 + rREG(%1)]
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%endmacro
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; Do palette/shade and translucency lookup
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%macro dotranspal 4 ; <tmp_reg> <tmp_reg_lobyte> <texel_reg> <dst_ofs>
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; Get palette index of the pixel in the frame buffer.
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; NOTE: e.g. "mov ah, byte [reg]" is not encodeable.
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movzx %1, byte [rDst + %4]
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shl %1, 8
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mov %2, byte [rAPalookup + %3] ; palette/shade
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mov %2, byte [rATransluc + %1] ; translucency
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%endmacro
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;;; ========== TVLINEASM1 ==========
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;;; TODO: transmode, nonpow2
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;;; Registers used in the loop
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%define rBpl r10
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%define rATransluc r12
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%define rVplc r11d
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;;; Registers of input args also used in the loop
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%define rVinc edi
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%define rAPalookup rsi
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%define rCnt edx
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%define rABufplc r8
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%define rDst r9
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;;; int32_t tvlineasm1(vinc, *paloffs, cnt, vplc, *bufplc, *p)
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;;; eax edi rsi edx ecx r8 r9
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ALIGN 16
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tvlineasm1:
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inc rCnt
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;; First, back up callee-saved registers and set up those used in the loop.
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PGET_rBpl
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mov rVplc, ecx
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GET_cl
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PGET_rATransluc
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push rbx
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jmp short tv1_loop
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ALIGN 16
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tv1_loop:
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gettexel bx, rABufplc, rVplc
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cmp bl, 255
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je short tv1_skiptrans
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dotranspal rax, al, rbx, 0
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mov byte [rDst], al
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tv1_skiptrans:
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add rVplc, rVinc
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add rDst, rBpl
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dec rCnt
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jnz short tv1_loop
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mov eax, rVplc ; return vplc
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pop rbx
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pop rATransluc
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pop rBpl
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ret
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;;; Undefine input arg macros
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%undef rVinc
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%undef rAPalookup
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%undef rCnt
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%undef rABufplc
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%undef rDst
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;;; Udefine rVplc register macro, but keep rBpl and rATransluc (r10 and r12).
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;;; Take care not to clash with them in the following.
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%undef rVplc
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;;; ========== TVLINEASM2 ==========
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;;; Registers used in the loop
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%define rVinc2 r11d
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%define rABufplc2 r13
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%define rDstEnd r14
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%define rAPalookup r15 ; TODO: second paloffs!
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;;; Registers of input args also used in the loop
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%define rVplc2 edi
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%define rVinc1 esi
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%define rABufplc1 rdx
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; bufplc2: rcx -> r13
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%define rVplc1 r8d
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%define rDst r9
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;;; Pass: asm1=vinc2, asm2=pend
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;;; Return: asm1=vplc1, asm2=vplc2
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;;; void tvlineasm2(vplc2, vinc1, *bufplc1, *bufplc2, vplc1, *p)
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;;; edi esi rdx rcx r8d r9
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ALIGN 16
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tvlineasm2:
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;; First, back up callee-saved registers and set up those used in the loop.
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mov rVinc2, dword [rel asm1]
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PGET_rBpl
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push rABufplc2
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mov rABufplc2, rcx
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GET_cl
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PGET_rATransluc
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push rDstEnd
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mov rDstEnd, [rel asm2]
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dec rDstEnd
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add rDstEnd, rBpl ; one more: compare with a-c.c's tvlineasm2()
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push rbx
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push rbp
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push rAPalookup
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mov rAPalookup, [rel a64_paloffs]
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jmp short tv2_loop
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ALIGN 16
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tv2_loop:
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gettexel bx, rABufplc1, rVplc1
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gettexel bp, rABufplc2, rVplc2
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mov eax, ebp
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shl eax, 8
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or eax, ebx
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cmp eax, 0xffff
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jz tv2_skiptrans
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dotranspal rax, al, rbx, 0
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dotranspal rbx, bl, rbp, 1
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and rax, 0xff
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shl rbx, 8
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or rax, rbx
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mov word [rDst], ax
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tv2_skiptrans:
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add rVplc1, rVinc1
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add rVplc2, rVinc2
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add rDst, rBpl
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cmp rDst, rDstEnd
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jnz tv2_loop
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pop r15
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pop rbp
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pop rbx
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pop rDstEnd
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pop rATransluc
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pop rABufplc2
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pop rBpl
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ret
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