mirror of
https://github.com/DrBeef/QuestZDoom.git
synced 2025-03-06 09:21:22 +00:00
186 lines
4.4 KiB
ArmAsm
186 lines
4.4 KiB
ArmAsm
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/*
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synth_stereo_neon64: NEON optimized synth for AArch64 (stereo specific version)
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copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
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see COPYING and AUTHORS files in distribution or http://mpg123.org
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initially written by Taihei Monma
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*/
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#include "mangle.h"
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#ifndef __APPLE__
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.section .rodata
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#else
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.data
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#endif
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ALIGN16
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maxmin_s16:
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.word 32767
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.word -32768
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.text
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ALIGN4
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.globl ASM_NAME(synth_1to1_s_neon64_asm)
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#ifdef __ELF__
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.type ASM_NAME(synth_1to1_s_neon64_asm), %function
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#endif
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ASM_NAME(synth_1to1_s_neon64_asm):
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add x0, x0, #32
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sub x0, x0, x4, lsl #1
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eor v30.16b, v30.16b, v30.16b
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adrp x5, AARCH64_PCREL_HI(maxmin_s16)
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add x5, x5, AARCH64_PCREL_LO(maxmin_s16)
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ld2r {v28.4s,v29.4s}, [x5]
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mov w4, #4
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mov x5, #64
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1:
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ld1 {v0.8h,v1.8h}, [x0], x5
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ld1 {v2.8h,v3.8h}, [x0], x5
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ld1 {v4.8h,v5.8h,v6.8h,v7.8h}, [x1], #64
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ld1 {v16.8h,v17.8h,v18.8h,v19.8h}, [x2], #64
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smull v24.4s, v0.4h, v4.4h
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smull v25.4s, v0.4h, v16.4h
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smull v26.4s, v2.4h, v6.4h
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smull v27.4s, v2.4h, v18.4h
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smlal2 v24.4s, v0.8h, v4.8h
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smlal2 v25.4s, v0.8h, v16.8h
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smlal2 v26.4s, v2.8h, v6.8h
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smlal2 v27.4s, v2.8h, v18.8h
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smlal v24.4s, v1.4h, v5.4h
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smlal v25.4s, v1.4h, v17.4h
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smlal v26.4s, v3.4h, v7.4h
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smlal v27.4s, v3.4h, v19.4h
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smlal2 v24.4s, v1.8h, v5.8h
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smlal2 v25.4s, v1.8h, v17.8h
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smlal2 v26.4s, v3.8h, v7.8h
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smlal2 v27.4s, v3.8h, v19.8h
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addp v0.4s, v24.4s, v25.4s
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addp v1.4s, v26.4s, v27.4s
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addp v0.4s, v0.4s, v1.4s
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sqrshrn v31.4h, v0.4s, #13
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cmgt v2.4s, v0.4s, v28.4s
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cmgt v3.4s, v29.4s, v0.4s
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add v2.4s, v2.4s, v3.4s
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add v30.4s, v30.4s, v2.4s
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ld1 {v0.8h,v1.8h}, [x0], x5
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ld1 {v2.8h,v3.8h}, [x0], x5
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ld1 {v4.8h,v5.8h,v6.8h,v7.8h}, [x1], #64
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ld1 {v16.8h,v17.8h,v18.8h,v19.8h}, [x2], #64
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smull v24.4s, v0.4h, v4.4h
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smull v25.4s, v0.4h, v16.4h
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smull v26.4s, v2.4h, v6.4h
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smull v27.4s, v2.4h, v18.4h
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smlal2 v24.4s, v0.8h, v4.8h
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smlal2 v25.4s, v0.8h, v16.8h
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smlal2 v26.4s, v2.8h, v6.8h
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smlal2 v27.4s, v2.8h, v18.8h
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smlal v24.4s, v1.4h, v5.4h
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smlal v25.4s, v1.4h, v17.4h
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smlal v26.4s, v3.4h, v7.4h
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smlal v27.4s, v3.4h, v19.4h
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smlal2 v24.4s, v1.8h, v5.8h
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smlal2 v25.4s, v1.8h, v17.8h
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smlal2 v26.4s, v3.8h, v7.8h
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smlal2 v27.4s, v3.8h, v19.8h
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addp v0.4s, v24.4s, v25.4s
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addp v1.4s, v26.4s, v27.4s
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addp v0.4s, v0.4s, v1.4s
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sqrshrn2 v31.8h, v0.4s, #13
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cmgt v2.4s, v0.4s, v28.4s
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cmgt v3.4s, v29.4s, v0.4s
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add v2.4s, v2.4s, v3.4s
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add v30.4s, v30.4s, v2.4s
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st1 {v31.4s}, [x3], #16
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subs w4, w4, #1
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b.ne 1b
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mov w4, #4
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mov x6, #-32
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2:
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ld1 {v0.8h,v1.8h}, [x0], x5
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ld1 {v2.8h,v3.8h}, [x0], x5
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ld1 {v4.8h,v5.8h}, [x1], x6
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ld1 {v6.8h,v7.8h}, [x1], x6
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ld1 {v16.8h,v17.8h}, [x2], x6
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ld1 {v18.8h,v19.8h}, [x2], x6
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smull v24.4s, v0.4h, v4.4h
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smull v25.4s, v0.4h, v16.4h
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smull v26.4s, v2.4h, v6.4h
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smull v27.4s, v2.4h, v18.4h
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smlal2 v24.4s, v0.8h, v4.8h
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smlal2 v25.4s, v0.8h, v16.8h
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smlal2 v26.4s, v2.8h, v6.8h
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smlal2 v27.4s, v2.8h, v18.8h
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smlal v24.4s, v1.4h, v5.4h
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smlal v25.4s, v1.4h, v17.4h
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smlal v26.4s, v3.4h, v7.4h
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smlal v27.4s, v3.4h, v19.4h
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smlal2 v24.4s, v1.8h, v5.8h
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smlal2 v25.4s, v1.8h, v17.8h
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smlal2 v26.4s, v3.8h, v7.8h
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smlal2 v27.4s, v3.8h, v19.8h
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addp v0.4s, v24.4s, v25.4s
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addp v1.4s, v26.4s, v27.4s
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addp v0.4s, v0.4s, v1.4s
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sqrshrn v31.4h, v0.4s, #13
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cmgt v2.4s, v0.4s, v28.4s
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cmgt v3.4s, v29.4s, v0.4s
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add v2.4s, v2.4s, v3.4s
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add v30.4s, v30.4s, v2.4s
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ld1 {v0.8h,v1.8h}, [x0], x5
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ld1 {v2.8h,v3.8h}, [x0], x5
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ld1 {v4.8h,v5.8h}, [x1], x6
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ld1 {v6.8h,v7.8h}, [x1], x6
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ld1 {v16.8h,v17.8h}, [x2], x6
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ld1 {v18.8h,v19.8h}, [x2], x6
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smull v24.4s, v0.4h, v4.4h
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smull v25.4s, v0.4h, v16.4h
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smull v26.4s, v2.4h, v6.4h
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smull v27.4s, v2.4h, v18.4h
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smlal2 v24.4s, v0.8h, v4.8h
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smlal2 v25.4s, v0.8h, v16.8h
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smlal2 v26.4s, v2.8h, v6.8h
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smlal2 v27.4s, v2.8h, v18.8h
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smlal v24.4s, v1.4h, v5.4h
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smlal v25.4s, v1.4h, v17.4h
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smlal v26.4s, v3.4h, v7.4h
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smlal v27.4s, v3.4h, v19.4h
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smlal2 v24.4s, v1.8h, v5.8h
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smlal2 v25.4s, v1.8h, v17.8h
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smlal2 v26.4s, v3.8h, v7.8h
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smlal2 v27.4s, v3.8h, v19.8h
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addp v0.4s, v24.4s, v25.4s
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addp v1.4s, v26.4s, v27.4s
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addp v0.4s, v0.4s, v1.4s
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sqrshrn2 v31.8h, v0.4s, #13
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cmgt v2.4s, v0.4s, v28.4s
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cmgt v3.4s, v29.4s, v0.4s
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add v2.4s, v2.4s, v3.4s
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add v30.4s, v30.4s, v2.4s
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st1 {v31.4s}, [x3], #16
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subs w4, w4, #1
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b.ne 2b
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AARCH64_DUP_2D(v0, v30, 1)
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add v0.4s, v0.4s, v30.4s
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AARCH64_DUP_4S(v1, v0, 1)
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add v0.4s, v0.4s, v1.4s
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umov w0, v0.s[0]
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neg w0, w0
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ret
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NONEXEC_STACK
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