mirror of
https://github.com/DrBeef/QuestZDoom.git
synced 2025-03-06 09:21:22 +00:00
250 lines
5.5 KiB
ArmAsm
250 lines
5.5 KiB
ArmAsm
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/*
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dct36_neon64: NEON optimized dct36 for AArch64
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copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
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see COPYING and AUTHORS files in distribution or http://mpg123.org
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initially written by Taihei Monma
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*/
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#include "mangle.h"
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#ifndef __APPLE__
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.section .rodata
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#else
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.data
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#endif
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ALIGN16
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dct36_aarch64_COS9:
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.word 0x3f5db3d7
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.word 0x3f5db3d7
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.word 0x3f000000
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.word 0x3f000000
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.word 0x3f7c1c5c
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.word 0x3f7c1c5c
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.word 0x3f708fb2
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.word 0x3f708fb2
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.word 0x3f248dbb
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.word 0x3f248dbb
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.word 0x3e31d0d4
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.word 0x3e31d0d4
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.word 0x3eaf1d44
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.word 0x3eaf1d44
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.word 0x3f441b7d
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.word 0x3f441b7d
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.word 0x3f007d2b
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.word 0x3f0483ee
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.word 0x3f0d3b7d
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.word 0x3f1c4257
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.word 0x40b79454
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.word 0x3ff746ea
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.word 0x3f976fd9
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.word 0x3f5f2944
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.word 0x3f800000
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.word 0x3f3504f3
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.text
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ALIGN4
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.globl ASM_NAME(dct36_neon64)
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#ifdef __ELF__
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.type ASM_NAME(dct36_neon64), %function
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#endif
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ASM_NAME(dct36_neon64):
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adrp x5, AARCH64_PCREL_HI(dct36_aarch64_COS9)
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add x5, x5, AARCH64_PCREL_LO(dct36_aarch64_COS9)
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cmeq v28.16b, v28.16b, v28.16b
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eor v29.16b, v29.16b, v29.16b
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shl v28.2d, v28.2d, #32
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ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], #64
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ld1 {v4.2s}, [x0]
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ext v16.16b, v29.16b, v0.16b, #12
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ext v17.16b, v0.16b, v1.16b, #12
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ext v18.16b, v1.16b, v2.16b, #12
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ext v19.16b, v2.16b, v3.16b, #12
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ext v20.16b, v3.16b, v4.16b, #12
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fadd v0.4s, v0.4s, v16.4s
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fadd v1.4s, v1.4s, v17.4s
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fadd v2.4s, v2.4s, v18.4s
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fadd v3.4s, v3.4s, v19.4s
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fadd v4.2s, v4.2s, v20.2s
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ext v16.16b, v0.16b, v1.16b, #8
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ext v17.16b, v1.16b, v2.16b, #8
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ext v18.16b, v2.16b, v3.16b, #8
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ext v19.16b, v3.16b, v4.16b, #8
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and v20.16b, v0.16b, v28.16b
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ext v0.16b, v29.16b, v0.16b, #8
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and v21.16b, v1.16b, v28.16b
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and v22.16b, v2.16b, v28.16b
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and v23.16b, v3.16b, v28.16b
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fadd v1.4s, v20.4s, v16.4s
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fadd v2.4s, v21.4s, v17.4s
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fadd v3.4s, v22.4s, v18.4s
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fadd v4.4s, v23.4s, v19.4s
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/*
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v0 in[-,-,0,1]
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v1 in[2,3,4,5]
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v2 in[6,7,8,9]
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v3 in[10,11,12,13]
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v4 in[14,15,16,17]
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*/
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orr v5.16b, v2.16b, v2.16b
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ins v2.d[1], v3.d[1]
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ins v3.d[1], v4.d[1]
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ins v4.d[1], v5.d[1]
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/*
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v2 in[6,7,12,13]
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v3 in[10,11,16,17]
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v4 in[14,15,8,9]
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*/
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ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x5], #64
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orr v20.16b, v0.16b, v0.16b
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fmla v20.4s, v2.4s, v16.4s
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/*
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v17 COS9_[1,1,2,2]
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v18 COS9_[5,5,8,8]
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v19 COS9_[7,7,4,4]
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v16 COS9_[3,3,6,6]
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v20 [ta33,tb33,ta66,tb66]
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*/
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orr v21.16b, v20.16b, v20.16b
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orr v23.16b, v20.16b, v20.16b
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zip2 v25.2d, v29.2d, v2.2d
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fsub v22.4s, v1.4s, v3.4s
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fmul v24.4s, v1.4s, v17.4s
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fmul v26.4s, v1.4s, v18.4s
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fmul v27.4s, v1.4s, v19.4s
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fmla v21.4s, v3.4s, v18.4s
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fmla v23.4s, v3.4s, v19.4s
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fmla v20.4s, v4.4s, v18.4s
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fsub v25.4s, v0.4s, v25.4s
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fsub v22.4s, v22.4s, v4.4s
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fmla v24.4s, v4.4s, v19.4s
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fmla v26.4s, v4.4s, v17.4s
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fmla v27.4s, v3.4s, v17.4s
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fmla v25.4s, v22.4s, v16.4s
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fadd v24.4s, v24.4s, v21.4s
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fsub v26.4s, v26.4s, v23.4s
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fsub v27.4s, v27.4s, v20.4s
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zip1 v16.4s, v24.4s, v25.4s
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zip2 v17.4s, v24.4s, v25.4s
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zip1 v18.4s, v26.4s, v27.4s
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zip2 v19.4s, v26.4s, v27.4s
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fneg v19.4s, v19.4s
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zip1 v20.2d, v16.2d, v18.2d
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zip1 v21.2d, v17.2d, v19.2d
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zip2 v22.2d, v16.2d, v18.2d
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zip2 v23.2d, v17.2d, v19.2d
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ld1 {v5.4s,v6.4s}, [x5], #32
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ld1 {v7.2s}, [x5]
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fsub v0.4s, v0.4s, v1.4s
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fsub v4.4s, v4.4s, v2.4s
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fadd v17.4s, v22.4s, v23.4s
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fsub v19.4s, v23.4s, v22.4s
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fadd v0.4s, v0.4s, v3.4s
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fadd v16.4s, v20.4s, v21.4s
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fsub v18.4s, v21.4s, v20.4s
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fadd v0.4s, v0.4s, v4.4s
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fmul v17.4s, v17.4s, v5.4s
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fmul v19.4s, v19.4s, v6.4s
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AARCH64_DUP_2D(v0, v0, 1)
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fmul v0.2s, v0.2s, v7.2s
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/*
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v16 tmp[0,1,2,3]
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v17 tmp[17,16,15,14]
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v18 tmp[8,7,6,5]
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v19 tmp[9,10,11,12]
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v0 tmp[4,13]
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*/
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add x0, x4, #640
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add x5, x3, #20
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add x6, x3, #92
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add x7, x1, #20
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ld1 {v1.4s,v2.4s}, [x5]
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ld1 {v3.4s,v4.4s}, [x6]
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ld1 {v5.4s,v6.4s}, [x7]
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fadd v20.4s, v16.4s, v17.4s
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fsub v21.4s, v16.4s, v17.4s
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fmul v4.4s, v20.4s, v4.4s
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fmla v6.4s, v21.4s, v2.4s
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rev64 v20.4s, v20.4s
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rev64 v21.4s, v21.4s
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ext v20.16b, v20.16b, v20.16b, #8
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ext v21.16b, v21.16b, v21.16b, #8
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fmul v3.4s, v20.4s, v3.4s
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fmla v5.4s, v21.4s, v1.4s
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add x5, x2, #20
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mov x9, #128
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st1 {v3.4s,v4.4s}, [x5]
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st1 {v5.s}[0], [x0], x9
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st1 {v5.s}[1], [x0], x9
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st1 {v5.s}[2], [x0], x9
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st1 {v5.s}[3], [x0], x9
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st1 {v6.s}[0], [x0], x9
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st1 {v6.s}[1], [x0], x9
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st1 {v6.s}[2], [x0], x9
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st1 {v6.s}[3], [x0], x9
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add x0, x4, #1792
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add x5, x3, #56
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add x6, x3, #128
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add x7, x1, #56
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ld1 {v1.4s}, [x3]
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ld1 {v2.4s,v3.4s}, [x5]
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ld1 {v4.4s}, [x6]
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ld1 {v5.4s}, [x1]
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ld1 {v6.4s}, [x7]
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fadd v20.4s, v18.4s, v19.4s
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fsub v21.4s, v18.4s, v19.4s
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fmul v3.4s, v20.4s, v3.4s
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fmla v5.4s, v21.4s, v1.4s
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rev64 v20.4s, v20.4s
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rev64 v21.4s, v21.4s
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ext v20.16b, v20.16b, v20.16b, #8
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ext v21.16b, v21.16b, v21.16b, #8
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fmul v4.4s, v20.4s, v4.4s
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fmla v6.4s, v21.4s, v2.4s
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add x5, x2, #56
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st1 {v3.4s}, [x2]
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st1 {v4.4s}, [x5]
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st1 {v5.s}[0], [x4], x9
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st1 {v5.s}[1], [x4], x9
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st1 {v5.s}[2], [x4], x9
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st1 {v5.s}[3], [x4], x9
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st1 {v6.s}[0], [x0], x9
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st1 {v6.s}[1], [x0], x9
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st1 {v6.s}[2], [x0], x9
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st1 {v6.s}[3], [x0], x9
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ins v1.s[0], v0.s[1]
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ldr s2, [x3, #16]
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ldr s3, [x3, #52]
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ldr s4, [x3, #88]
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ldr s5, [x3, #124]
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ldr s6, [x1, #16]
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ldr s7, [x1, #52]
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fadd s16, s0, s1
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fsub s17, s0, s1
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fmul s4, s16, s4
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fmul s5, s16, s5
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fmadd s6, s17, s2, s6
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fmadd s7, s17, s3, s7
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str s4, [x2, #16]
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str s5, [x2, #52]
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str s6, [x4]
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str s7, [x4, #1152]
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ret
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NONEXEC_STACK
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