mirror of
https://git.code.sf.net/p/quake/quakeforge
synced 2025-03-13 14:12:02 +00:00
b2a1a3c791
I got a sync validation error on a scatter command (I think) thus the setting was probably wrong. Most of the parameters are still what they were, but I'll be able to tweak the barriers as necessary. Unfortunately, it didn't help with the hang on fetching the light cull query data when starting in fisheye mode (no hang when enabling fisheye after startup). I'm not sure what's going on there other than the queries aren't getting updated: the counts seem to be fine so maybe the commands aren't running. I've probably got a tangled mess of pseudo-parallel command buffers: I need to go through my system and clean everything up.
318 lines
11 KiB
C
318 lines
11 KiB
C
/*
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barrier.c
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Memory barrier helpers
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Copyright (C) 2021 Bill Currie <bill@taniwha.org>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to:
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Free Software Foundation, Inc.
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59 Temple Place - Suite 330
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Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CONFIG_H
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# include "config.h"
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#endif
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#include "QF/Vulkan/barrier.h"
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const qfv_imagebarrier_t imageBarriers[] = {
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[qfv_LT_Undefined_to_TransferDst] = {
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.srcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_IMAGE_LAYOUT_UNDEFINED,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_Undefined_to_General] = {
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.srcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_IMAGE_LAYOUT_UNDEFINED,
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VK_IMAGE_LAYOUT_GENERAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_Undefined_to_ShaderReadOnly] = {
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.srcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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0,
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VK_ACCESS_SHADER_READ_BIT,
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VK_IMAGE_LAYOUT_UNDEFINED,
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VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_TransferDst_to_TransferDst] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_TransferDst_to_TransferSrc] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_ACCESS_TRANSFER_READ_BIT,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_TransferDst_to_General] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_IMAGE_LAYOUT_GENERAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_TransferDst_to_ShaderReadOnly] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_TransferSrc_to_ShaderReadOnly] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_READ_BIT,
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VK_ACCESS_SHADER_READ_BIT,
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VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL,
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VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_ShaderReadOnly_to_TransferDst] = {
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.srcStages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_READ_BIT,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_Undefined_to_DepthStencil] = {
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.srcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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0,
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VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
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VK_IMAGE_LAYOUT_UNDEFINED,
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VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_DEPTH_BIT, 0, 1, 0, 1 }
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},
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},
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[qfv_LT_Undefined_to_Color] = {
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.srcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, 0,
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0,
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VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT,
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VK_IMAGE_LAYOUT_UNDEFINED,
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VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED, 0,
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{ VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }
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},
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},
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};
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const qfv_bufferbarrier_t bufferBarriers[] = {
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[qfv_BB_Unknown_to_TransferWrite] = {
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.srcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.dstAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_UniformRead_to_TransferWrite] = {
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.srcStages = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.dstAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_VertexAttrRead_to_TransferWrite] = {
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.srcStages = VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
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.dstStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.barrier = {
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.srcAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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.dstAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_TransferWrite_to_VertexAttrRead] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
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.barrier = {
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_TransferWrite_to_IndexRead] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_WRITE_BIT, VK_ACCESS_INDEX_READ_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_TransferWrite_to_UniformRead] = {
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// note: not necessarily optimal as it uses vertex shader for dst
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_VERTEX_SHADER_BIT,
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.barrier = {
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_UNIFORM_READ_BIT
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| VK_ACCESS_SHADER_READ_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_TransferWrite_to_ShaderRW] = {
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.srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT,
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.dstStages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_TRANSFER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_ShaderRW_to_ShaderRO] = {
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.srcStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.dstStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_ShaderRW_to_ShaderRO_VA] = {
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.srcStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.dstStages = VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
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| VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_ShaderRO_to_ShaderWrite] = {
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.srcStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.dstStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_READ_BIT,
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VK_ACCESS_SHADER_WRITE_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_ShaderRO_VA_to_ShaderWrite] = {
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.srcStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
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| VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
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.dstStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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VK_ACCESS_SHADER_WRITE_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_ShaderWrite_to_ShaderRO] = {
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.srcStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.dstStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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[qfv_BB_ShaderWrite_to_ShaderRW] = {
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.srcStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.dstStages = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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.barrier = {
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VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER, 0,
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VK_ACCESS_SHADER_WRITE_BIT,
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VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
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VK_QUEUE_FAMILY_IGNORED, VK_QUEUE_FAMILY_IGNORED,
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},
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},
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};
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