mirror of
https://github.com/ioquake/ioq3.git
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03201aff22
- Clean up ftol()/snapvector() mess - Make use of SSE instructions for ftol()/snapvector() if available - move ftol/snapvector pure assembler to inline assembler, this will add x86_64 and improve support for different calling conventions - Set FPU control word at program startup to get consistent behaviour on all platforms
107 lines
2.9 KiB
NASM
107 lines
2.9 KiB
NASM
; ===========================================================================
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; Copyright (C) 2011 Thilo Schulz <thilo@tjps.eu>
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;
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; This file is part of Quake III Arena source code.
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;
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; Quake III Arena source code is free software; you can redistribute it
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; and/or modify it under the terms of the GNU General Public License as
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; published by the Free Software Foundation; either version 2 of the License,
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; or (at your option) any later version.
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;
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; Quake III Arena source code is distributed in the hope that it will be
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; useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with Quake III Arena source code; if not, write to the Free Software
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; Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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; ===========================================================================
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; MASM version of snapvector conversion function using SSE or FPU
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; assume __cdecl calling convention is being used for x86, __fastcall for x64
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;
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; function prototype:
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; void qsnapvector(vec3_t vec)
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IFNDEF idx64
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.model flat, c
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ENDIF
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.data
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ALIGN 16
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ssemask DWORD 0FFFFFFFFh, 0FFFFFFFFh, 0FFFFFFFFh, 00000000h
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ssecw DWORD 00001F80h
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IFNDEF idx64
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fpucw WORD 037Fh
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ENDIF
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.code
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IFDEF idx64
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; qsnapvector using SSE
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qsnapvectorsse PROC
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sub rsp, 4
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stmxcsr [rsp] ; save SSE control word
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ldmxcsr ssecw ; set to round nearest
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push rdi
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mov rdi, rcx ; maskmovdqu uses rdi as implicit memory operand
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movaps xmm1, ssemask ; initialize the mask register for maskmovdqu
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movups xmm0, [rdi] ; here is stored our vector. Read 4 values in one go
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cvtps2dq xmm0, xmm0 ; convert 4 single fp to int
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cvtdq2ps xmm0, xmm0 ; convert 4 int to single fp
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maskmovdqu xmm0, xmm1 ; write 3 values back to memory
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pop rdi
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ldmxcsr [rsp] ; restore sse control word to old value
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add rsp, 4
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ret
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qsnapvectorsse ENDP
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ELSE
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qsnapvectorsse PROC
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sub esp, 4
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stmxcsr [esp] ; save SSE control word
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ldmxcsr ssecw ; set to round nearest
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push edi
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mov edi, dword ptr 12[esp] ; maskmovdqu uses edi as implicit memory operand
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movaps xmm1, ssemask ; initialize the mask register for maskmovdqu
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movups xmm0, [edi] ; here is stored our vector. Read 4 values in one go
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cvtps2dq xmm0, xmm0 ; convert 4 single fp to int
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cvtdq2ps xmm0, xmm0 ; convert 4 int to single fp
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maskmovdqu xmm0, xmm1 ; write 3 values back to memory
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pop edi
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ldmxcsr [esp] ; restore sse control word to old value
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add esp, 4
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ret
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qsnapvectorsse ENDP
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qroundx87 macro src
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fld dword ptr src
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fistp dword ptr src
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fild dword ptr src
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fstp dword ptr src
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endm
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qsnapvectorx87 PROC
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mov eax, dword ptr 4[esp]
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sub esp, 2
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fnstcw word ptr [esp]
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fldcw fpucw
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qroundx87 [eax]
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qroundx87 4[eax]
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qroundx87 8[eax]
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fldcw [esp]
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add esp, 2
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qsnapvectorx87 ENDP
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ENDIF
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end
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