mirror of
https://github.com/id-Software/DOOM-3-BFG.git
synced 2024-11-25 05:21:39 +00:00
1105 lines
24 KiB
C++
1105 lines
24 KiB
C++
/*
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===========================================================================
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Doom 3 BFG Edition GPL Source Code
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Copyright (C) 1993-2012 id Software LLC, a ZeniMax Media company.
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This file is part of the Doom 3 BFG Edition GPL Source Code ("Doom 3 BFG Edition Source Code").
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Doom 3 BFG Edition Source Code is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Doom 3 BFG Edition Source Code is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Doom 3 BFG Edition Source Code. If not, see <http://www.gnu.org/licenses/>.
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In addition, the Doom 3 BFG Edition Source Code is also subject to certain additional terms. You should have received a copy of these additional terms immediately following the terms and conditions of the GNU General Public License which accompanied the Doom 3 BFG Edition Source Code. If not, please request a copy in writing from id Software at the address below.
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If you have questions concerning this license or the applicable additional terms, you may contact in writing id Software LLC, c/o ZeniMax Media Inc., Suite 120, Rockville, Maryland 20850 USA.
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===========================================================================
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*/
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#pragma hdrstop
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#include "../../idlib/precompiled.h"
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#include "win_local.h"
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#pragma warning(disable:4740) // warning C4740: flow in or out of inline asm code suppresses global optimization
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#pragma warning(disable:4731) // warning C4731: 'XXX' : frame pointer register 'ebx' modified by inline assembly code
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/*
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==============================================================
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Clock ticks
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==============================================================
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*/
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/*
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================
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Sys_GetClockTicks
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================
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*/
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double Sys_GetClockTicks() {
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#if 0
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LARGE_INTEGER li;
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QueryPerformanceCounter( &li );
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return = (double ) li.LowPart + (double) 0xFFFFFFFF * li.HighPart;
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#else
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unsigned long lo, hi;
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__asm {
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push ebx
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xor eax, eax
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cpuid
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rdtsc
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mov lo, eax
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mov hi, edx
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pop ebx
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}
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return (double ) lo + (double) 0xFFFFFFFF * hi;
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#endif
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}
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/*
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================
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Sys_ClockTicksPerSecond
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================
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*/
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double Sys_ClockTicksPerSecond() {
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static double ticks = 0;
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#if 0
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if ( !ticks ) {
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LARGE_INTEGER li;
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QueryPerformanceFrequency( &li );
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ticks = li.QuadPart;
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}
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#else
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if ( !ticks ) {
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HKEY hKey;
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LPBYTE ProcSpeed;
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DWORD buflen, ret;
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if ( !RegOpenKeyEx( HKEY_LOCAL_MACHINE, "HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0", 0, KEY_READ, &hKey ) ) {
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ProcSpeed = 0;
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buflen = sizeof( ProcSpeed );
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ret = RegQueryValueEx( hKey, "~MHz", NULL, NULL, (LPBYTE) &ProcSpeed, &buflen );
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// If we don't succeed, try some other spellings.
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if ( ret != ERROR_SUCCESS ) {
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ret = RegQueryValueEx( hKey, "~Mhz", NULL, NULL, (LPBYTE) &ProcSpeed, &buflen );
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}
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if ( ret != ERROR_SUCCESS ) {
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ret = RegQueryValueEx( hKey, "~mhz", NULL, NULL, (LPBYTE) &ProcSpeed, &buflen );
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}
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RegCloseKey( hKey );
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if ( ret == ERROR_SUCCESS ) {
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ticks = (double) ((unsigned long)ProcSpeed) * 1000000;
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}
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}
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}
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#endif
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return ticks;
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}
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/*
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==============================================================
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CPU
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==============================================================
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*/
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/*
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================
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HasCPUID
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================
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*/
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static bool HasCPUID() {
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__asm
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{
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pushfd // save eflags
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pop eax
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test eax, 0x00200000 // check ID bit
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jz set21 // bit 21 is not set, so jump to set_21
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and eax, 0xffdfffff // clear bit 21
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push eax // save new value in register
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popfd // store new value in flags
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pushfd
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pop eax
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test eax, 0x00200000 // check ID bit
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jz good
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jmp err // cpuid not supported
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set21:
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or eax, 0x00200000 // set ID bit
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push eax // store new value
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popfd // store new value in EFLAGS
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pushfd
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pop eax
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test eax, 0x00200000 // if bit 21 is on
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jnz good
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jmp err
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}
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err:
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return false;
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good:
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return true;
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}
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#define _REG_EAX 0
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#define _REG_EBX 1
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#define _REG_ECX 2
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#define _REG_EDX 3
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/*
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================
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CPUID
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================
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*/
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static void CPUID( int func, unsigned regs[4] ) {
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unsigned regEAX, regEBX, regECX, regEDX;
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__asm pusha
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__asm mov eax, func
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__asm __emit 00fh
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__asm __emit 0a2h
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__asm mov regEAX, eax
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__asm mov regEBX, ebx
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__asm mov regECX, ecx
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__asm mov regEDX, edx
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__asm popa
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regs[_REG_EAX] = regEAX;
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regs[_REG_EBX] = regEBX;
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regs[_REG_ECX] = regECX;
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regs[_REG_EDX] = regEDX;
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}
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/*
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================
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IsAMD
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================
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*/
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static bool IsAMD() {
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char pstring[16];
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char processorString[13];
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// get name of processor
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CPUID( 0, ( unsigned int * ) pstring );
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processorString[0] = pstring[4];
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processorString[1] = pstring[5];
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processorString[2] = pstring[6];
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processorString[3] = pstring[7];
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processorString[4] = pstring[12];
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processorString[5] = pstring[13];
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processorString[6] = pstring[14];
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processorString[7] = pstring[15];
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processorString[8] = pstring[8];
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processorString[9] = pstring[9];
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processorString[10] = pstring[10];
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processorString[11] = pstring[11];
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processorString[12] = 0;
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if ( strcmp( processorString, "AuthenticAMD" ) == 0 ) {
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return true;
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}
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return false;
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}
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/*
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================
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HasCMOV
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================
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*/
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static bool HasCMOV() {
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unsigned regs[4];
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// get CPU feature bits
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CPUID( 1, regs );
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// bit 15 of EDX denotes CMOV existence
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if ( regs[_REG_EDX] & ( 1 << 15 ) ) {
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return true;
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}
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return false;
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}
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/*
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================
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Has3DNow
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================
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*/
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static bool Has3DNow() {
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unsigned regs[4];
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// check AMD-specific functions
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CPUID( 0x80000000, regs );
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if ( regs[_REG_EAX] < 0x80000000 ) {
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return false;
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}
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// bit 31 of EDX denotes 3DNow! support
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CPUID( 0x80000001, regs );
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if ( regs[_REG_EDX] & ( 1 << 31 ) ) {
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return true;
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}
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return false;
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}
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/*
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================
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HasMMX
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================
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*/
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static bool HasMMX() {
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unsigned regs[4];
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// get CPU feature bits
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CPUID( 1, regs );
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// bit 23 of EDX denotes MMX existence
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if ( regs[_REG_EDX] & ( 1 << 23 ) ) {
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return true;
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}
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return false;
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}
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/*
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================
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HasSSE
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================
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*/
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static bool HasSSE() {
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unsigned regs[4];
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// get CPU feature bits
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CPUID( 1, regs );
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// bit 25 of EDX denotes SSE existence
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if ( regs[_REG_EDX] & ( 1 << 25 ) ) {
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return true;
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}
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return false;
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}
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/*
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================
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HasSSE2
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================
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*/
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static bool HasSSE2() {
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unsigned regs[4];
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// get CPU feature bits
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CPUID( 1, regs );
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// bit 26 of EDX denotes SSE2 existence
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if ( regs[_REG_EDX] & ( 1 << 26 ) ) {
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return true;
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}
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return false;
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}
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/*
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================
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HasSSE3
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================
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*/
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static bool HasSSE3() {
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unsigned regs[4];
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// get CPU feature bits
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CPUID( 1, regs );
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// bit 0 of ECX denotes SSE3 existence
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if ( regs[_REG_ECX] & ( 1 << 0 ) ) {
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return true;
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}
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return false;
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}
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/*
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================
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LogicalProcPerPhysicalProc
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================
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*/
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#define NUM_LOGICAL_BITS 0x00FF0000 // EBX[23:16] Bit 16-23 in ebx contains the number of logical
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// processors per physical processor when execute cpuid with
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// eax set to 1
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static unsigned char LogicalProcPerPhysicalProc() {
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unsigned int regebx = 0;
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__asm {
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mov eax, 1
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cpuid
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mov regebx, ebx
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}
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return (unsigned char) ((regebx & NUM_LOGICAL_BITS) >> 16);
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}
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/*
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================
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GetAPIC_ID
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================
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*/
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#define INITIAL_APIC_ID_BITS 0xFF000000 // EBX[31:24] Bits 24-31 (8 bits) return the 8-bit unique
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// initial APIC ID for the processor this code is running on.
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// Default value = 0xff if HT is not supported
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static unsigned char GetAPIC_ID() {
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unsigned int regebx = 0;
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__asm {
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mov eax, 1
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cpuid
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mov regebx, ebx
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}
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return (unsigned char) ((regebx & INITIAL_APIC_ID_BITS) >> 24);
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}
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/*
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================
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CPUCount
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logicalNum is the number of logical CPU per physical CPU
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physicalNum is the total number of physical processor
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returns one of the HT_* flags
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================
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*/
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#define HT_NOT_CAPABLE 0
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#define HT_ENABLED 1
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#define HT_DISABLED 2
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#define HT_SUPPORTED_NOT_ENABLED 3
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#define HT_CANNOT_DETECT 4
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int CPUCount( int &logicalNum, int &physicalNum ) {
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int statusFlag;
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SYSTEM_INFO info;
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physicalNum = 1;
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logicalNum = 1;
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statusFlag = HT_NOT_CAPABLE;
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info.dwNumberOfProcessors = 0;
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GetSystemInfo (&info);
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// Number of physical processors in a non-Intel system
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// or in a 32-bit Intel system with Hyper-Threading technology disabled
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physicalNum = info.dwNumberOfProcessors;
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unsigned char HT_Enabled = 0;
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logicalNum = LogicalProcPerPhysicalProc();
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if ( logicalNum >= 1 ) { // > 1 doesn't mean HT is enabled in the BIOS
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HANDLE hCurrentProcessHandle;
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DWORD dwProcessAffinity;
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DWORD dwSystemAffinity;
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DWORD dwAffinityMask;
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// Calculate the appropriate shifts and mask based on the
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// number of logical processors.
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unsigned char i = 1, PHY_ID_MASK = 0xFF, PHY_ID_SHIFT = 0;
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while( i < logicalNum ) {
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i *= 2;
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PHY_ID_MASK <<= 1;
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PHY_ID_SHIFT++;
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}
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hCurrentProcessHandle = GetCurrentProcess();
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GetProcessAffinityMask( hCurrentProcessHandle, &dwProcessAffinity, &dwSystemAffinity );
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// Check if available process affinity mask is equal to the
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// available system affinity mask
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if ( dwProcessAffinity != dwSystemAffinity ) {
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statusFlag = HT_CANNOT_DETECT;
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physicalNum = -1;
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return statusFlag;
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}
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dwAffinityMask = 1;
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while ( dwAffinityMask != 0 && dwAffinityMask <= dwProcessAffinity ) {
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// Check if this CPU is available
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if ( dwAffinityMask & dwProcessAffinity ) {
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if ( SetProcessAffinityMask( hCurrentProcessHandle, dwAffinityMask ) ) {
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unsigned char APIC_ID, LOG_ID, PHY_ID;
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Sleep( 0 ); // Give OS time to switch CPU
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APIC_ID = GetAPIC_ID();
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LOG_ID = APIC_ID & ~PHY_ID_MASK;
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PHY_ID = APIC_ID >> PHY_ID_SHIFT;
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if ( LOG_ID != 0 ) {
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HT_Enabled = 1;
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}
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}
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}
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dwAffinityMask = dwAffinityMask << 1;
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}
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// Reset the processor affinity
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SetProcessAffinityMask( hCurrentProcessHandle, dwProcessAffinity );
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if ( logicalNum == 1 ) { // Normal P4 : HT is disabled in hardware
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statusFlag = HT_DISABLED;
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} else {
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if ( HT_Enabled ) {
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// Total physical processors in a Hyper-Threading enabled system.
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physicalNum /= logicalNum;
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statusFlag = HT_ENABLED;
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} else {
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statusFlag = HT_SUPPORTED_NOT_ENABLED;
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}
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}
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}
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return statusFlag;
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}
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|
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/*
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================
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HasHTT
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================
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*/
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static bool HasHTT() {
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unsigned regs[4];
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int logicalNum, physicalNum, HTStatusFlag;
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// get CPU feature bits
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CPUID( 1, regs );
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// bit 28 of EDX denotes HTT existence
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if ( !( regs[_REG_EDX] & ( 1 << 28 ) ) ) {
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return false;
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}
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HTStatusFlag = CPUCount( logicalNum, physicalNum );
|
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if ( HTStatusFlag != HT_ENABLED ) {
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return false;
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}
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return true;
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}
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|
|
/*
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|
================
|
|
HasHTT
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================
|
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*/
|
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static bool HasDAZ() {
|
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__declspec(align(16)) unsigned char FXSaveArea[512];
|
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unsigned char *FXArea = FXSaveArea;
|
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DWORD dwMask = 0;
|
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unsigned regs[4];
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|
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// get CPU feature bits
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CPUID( 1, regs );
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|
|
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// bit 24 of EDX denotes support for FXSAVE
|
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if ( !( regs[_REG_EDX] & ( 1 << 24 ) ) ) {
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return false;
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}
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|
|
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memset( FXArea, 0, sizeof( FXSaveArea ) );
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|
|
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__asm {
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mov eax, FXArea
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FXSAVE [eax]
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}
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|
|
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dwMask = *(DWORD *)&FXArea[28]; // Read the MXCSR Mask
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return ( ( dwMask & ( 1 << 6 ) ) == ( 1 << 6 ) ); // Return if the DAZ bit is set
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}
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|
|
|
/*
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|
================================================================================================
|
|
|
|
CPU
|
|
|
|
================================================================================================
|
|
*/
|
|
|
|
/*
|
|
========================
|
|
CountSetBits
|
|
Helper function to count set bits in the processor mask.
|
|
========================
|
|
*/
|
|
DWORD CountSetBits( ULONG_PTR bitMask ) {
|
|
DWORD LSHIFT = sizeof( ULONG_PTR ) * 8 - 1;
|
|
DWORD bitSetCount = 0;
|
|
ULONG_PTR bitTest = (ULONG_PTR)1 << LSHIFT;
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|
|
|
for ( DWORD i = 0; i <= LSHIFT; i++ ) {
|
|
bitSetCount += ( ( bitMask & bitTest ) ? 1 : 0 );
|
|
bitTest /= 2;
|
|
}
|
|
|
|
return bitSetCount;
|
|
}
|
|
|
|
typedef BOOL (WINAPI *LPFN_GLPI)( PSYSTEM_LOGICAL_PROCESSOR_INFORMATION, PDWORD );
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|
|
|
enum LOGICAL_PROCESSOR_RELATIONSHIP_LOCAL {
|
|
localRelationProcessorCore,
|
|
localRelationNumaNode,
|
|
localRelationCache,
|
|
localRelationProcessorPackage
|
|
};
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|
|
|
struct cpuInfo_t {
|
|
int processorPackageCount;
|
|
int processorCoreCount;
|
|
int logicalProcessorCount;
|
|
int numaNodeCount;
|
|
struct cacheInfo_t {
|
|
int count;
|
|
int associativity;
|
|
int lineSize;
|
|
int size;
|
|
} cacheLevel[3];
|
|
};
|
|
|
|
/*
|
|
========================
|
|
GetCPUInfo
|
|
========================
|
|
*/
|
|
bool GetCPUInfo( cpuInfo_t & cpuInfo ) {
|
|
PSYSTEM_LOGICAL_PROCESSOR_INFORMATION buffer = NULL;
|
|
PSYSTEM_LOGICAL_PROCESSOR_INFORMATION ptr = NULL;
|
|
PCACHE_DESCRIPTOR Cache;
|
|
LPFN_GLPI glpi;
|
|
BOOL done = FALSE;
|
|
DWORD returnLength = 0;
|
|
DWORD byteOffset = 0;
|
|
|
|
memset( & cpuInfo, 0, sizeof( cpuInfo ) );
|
|
|
|
glpi = (LPFN_GLPI)GetProcAddress( GetModuleHandle(TEXT("kernel32")), "GetLogicalProcessorInformation" );
|
|
if ( NULL == glpi ) {
|
|
idLib::Printf( "\nGetLogicalProcessorInformation is not supported.\n" );
|
|
return 0;
|
|
}
|
|
|
|
while ( !done ) {
|
|
DWORD rc = glpi( buffer, &returnLength );
|
|
|
|
if ( FALSE == rc ) {
|
|
if ( GetLastError() == ERROR_INSUFFICIENT_BUFFER ) {
|
|
if ( buffer ) {
|
|
free( buffer );
|
|
}
|
|
|
|
buffer = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION)malloc( returnLength );
|
|
} else {
|
|
idLib::Printf( "Sys_CPUCount error: %d\n", GetLastError() );
|
|
return false;
|
|
}
|
|
} else {
|
|
done = TRUE;
|
|
}
|
|
}
|
|
|
|
ptr = buffer;
|
|
|
|
while ( byteOffset + sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION) <= returnLength ) {
|
|
switch ( (LOGICAL_PROCESSOR_RELATIONSHIP_LOCAL) ptr->Relationship ) {
|
|
case localRelationProcessorCore:
|
|
cpuInfo.processorCoreCount++;
|
|
|
|
// A hyperthreaded core supplies more than one logical processor.
|
|
cpuInfo.logicalProcessorCount += CountSetBits( ptr->ProcessorMask );
|
|
break;
|
|
|
|
case localRelationNumaNode:
|
|
// Non-NUMA systems report a single record of this type.
|
|
cpuInfo.numaNodeCount++;
|
|
break;
|
|
|
|
case localRelationCache:
|
|
// Cache data is in ptr->Cache, one CACHE_DESCRIPTOR structure for each cache.
|
|
Cache = &ptr->Cache;
|
|
if ( Cache->Level >= 1 && Cache->Level <= 3 ) {
|
|
int level = Cache->Level - 1;
|
|
if ( cpuInfo.cacheLevel[level].count > 0 ) {
|
|
cpuInfo.cacheLevel[level].count++;
|
|
} else {
|
|
cpuInfo.cacheLevel[level].associativity = Cache->Associativity;
|
|
cpuInfo.cacheLevel[level].lineSize = Cache->LineSize;
|
|
cpuInfo.cacheLevel[level].size = Cache->Size;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case localRelationProcessorPackage:
|
|
// Logical processors share a physical package.
|
|
cpuInfo.processorPackageCount++;
|
|
break;
|
|
|
|
default:
|
|
idLib::Printf( "Error: Unsupported LOGICAL_PROCESSOR_RELATIONSHIP value.\n" );
|
|
break;
|
|
}
|
|
byteOffset += sizeof( SYSTEM_LOGICAL_PROCESSOR_INFORMATION );
|
|
ptr++;
|
|
}
|
|
|
|
free( buffer );
|
|
|
|
return true;
|
|
}
|
|
|
|
/*
|
|
========================
|
|
Sys_GetCPUCacheSize
|
|
========================
|
|
*/
|
|
void Sys_GetCPUCacheSize( int level, int & count, int & size, int & lineSize ) {
|
|
assert( level >= 1 && level <= 3 );
|
|
cpuInfo_t cpuInfo;
|
|
|
|
GetCPUInfo( cpuInfo );
|
|
|
|
count = cpuInfo.cacheLevel[level - 1].count;
|
|
size = cpuInfo.cacheLevel[level - 1].size;
|
|
lineSize = cpuInfo.cacheLevel[level - 1].lineSize;
|
|
}
|
|
|
|
/*
|
|
========================
|
|
Sys_CPUCount
|
|
|
|
numLogicalCPUCores - the number of logical CPU per core
|
|
numPhysicalCPUCores - the total number of cores per package
|
|
numCPUPackages - the total number of packages (physical processors)
|
|
========================
|
|
*/
|
|
void Sys_CPUCount( int & numLogicalCPUCores, int & numPhysicalCPUCores, int & numCPUPackages ) {
|
|
cpuInfo_t cpuInfo;
|
|
GetCPUInfo( cpuInfo );
|
|
|
|
numPhysicalCPUCores = cpuInfo.processorCoreCount;
|
|
numLogicalCPUCores = cpuInfo.logicalProcessorCount;
|
|
numCPUPackages = cpuInfo.processorPackageCount;
|
|
}
|
|
|
|
/*
|
|
================
|
|
Sys_GetCPUId
|
|
================
|
|
*/
|
|
cpuid_t Sys_GetCPUId() {
|
|
int flags;
|
|
|
|
// verify we're at least a Pentium or 486 with CPUID support
|
|
if ( !HasCPUID() ) {
|
|
return CPUID_UNSUPPORTED;
|
|
}
|
|
|
|
// check for an AMD
|
|
if ( IsAMD() ) {
|
|
flags = CPUID_AMD;
|
|
} else {
|
|
flags = CPUID_INTEL;
|
|
}
|
|
|
|
// check for Multi Media Extensions
|
|
if ( HasMMX() ) {
|
|
flags |= CPUID_MMX;
|
|
}
|
|
|
|
// check for 3DNow!
|
|
if ( Has3DNow() ) {
|
|
flags |= CPUID_3DNOW;
|
|
}
|
|
|
|
// check for Streaming SIMD Extensions
|
|
if ( HasSSE() ) {
|
|
flags |= CPUID_SSE | CPUID_FTZ;
|
|
}
|
|
|
|
// check for Streaming SIMD Extensions 2
|
|
if ( HasSSE2() ) {
|
|
flags |= CPUID_SSE2;
|
|
}
|
|
|
|
// check for Streaming SIMD Extensions 3 aka Prescott's New Instructions
|
|
if ( HasSSE3() ) {
|
|
flags |= CPUID_SSE3;
|
|
}
|
|
|
|
// check for Hyper-Threading Technology
|
|
if ( HasHTT() ) {
|
|
flags |= CPUID_HTT;
|
|
}
|
|
|
|
// check for Conditional Move (CMOV) and fast floating point comparison (FCOMI) instructions
|
|
if ( HasCMOV() ) {
|
|
flags |= CPUID_CMOV;
|
|
}
|
|
|
|
// check for Denormals-Are-Zero mode
|
|
if ( HasDAZ() ) {
|
|
flags |= CPUID_DAZ;
|
|
}
|
|
|
|
return (cpuid_t)flags;
|
|
}
|
|
|
|
|
|
/*
|
|
===============================================================================
|
|
|
|
FPU
|
|
|
|
===============================================================================
|
|
*/
|
|
|
|
typedef struct bitFlag_s {
|
|
char * name;
|
|
int bit;
|
|
} bitFlag_t;
|
|
|
|
static byte fpuState[128], *statePtr = fpuState;
|
|
static char fpuString[2048];
|
|
static bitFlag_t controlWordFlags[] = {
|
|
{ "Invalid operation", 0 },
|
|
{ "Denormalized operand", 1 },
|
|
{ "Divide-by-zero", 2 },
|
|
{ "Numeric overflow", 3 },
|
|
{ "Numeric underflow", 4 },
|
|
{ "Inexact result (precision)", 5 },
|
|
{ "Infinity control", 12 },
|
|
{ "", 0 }
|
|
};
|
|
static char *precisionControlField[] = {
|
|
"Single Precision (24-bits)",
|
|
"Reserved",
|
|
"Double Precision (53-bits)",
|
|
"Double Extended Precision (64-bits)"
|
|
};
|
|
static char *roundingControlField[] = {
|
|
"Round to nearest",
|
|
"Round down",
|
|
"Round up",
|
|
"Round toward zero"
|
|
};
|
|
static bitFlag_t statusWordFlags[] = {
|
|
{ "Invalid operation", 0 },
|
|
{ "Denormalized operand", 1 },
|
|
{ "Divide-by-zero", 2 },
|
|
{ "Numeric overflow", 3 },
|
|
{ "Numeric underflow", 4 },
|
|
{ "Inexact result (precision)", 5 },
|
|
{ "Stack fault", 6 },
|
|
{ "Error summary status", 7 },
|
|
{ "FPU busy", 15 },
|
|
{ "", 0 }
|
|
};
|
|
|
|
/*
|
|
===============
|
|
Sys_FPU_PrintStateFlags
|
|
===============
|
|
*/
|
|
int Sys_FPU_PrintStateFlags( char *ptr, int ctrl, int stat, int tags, int inof, int inse, int opof, int opse ) {
|
|
int i, length = 0;
|
|
|
|
length += sprintf( ptr+length, "CTRL = %08x\n"
|
|
"STAT = %08x\n"
|
|
"TAGS = %08x\n"
|
|
"INOF = %08x\n"
|
|
"INSE = %08x\n"
|
|
"OPOF = %08x\n"
|
|
"OPSE = %08x\n"
|
|
"\n",
|
|
ctrl, stat, tags, inof, inse, opof, opse );
|
|
|
|
length += sprintf( ptr+length, "Control Word:\n" );
|
|
for ( i = 0; controlWordFlags[i].name[0]; i++ ) {
|
|
length += sprintf( ptr+length, " %-30s = %s\n", controlWordFlags[i].name, ( ctrl & ( 1 << controlWordFlags[i].bit ) ) ? "true" : "false" );
|
|
}
|
|
length += sprintf( ptr+length, " %-30s = %s\n", "Precision control", precisionControlField[(ctrl>>8)&3] );
|
|
length += sprintf( ptr+length, " %-30s = %s\n", "Rounding control", roundingControlField[(ctrl>>10)&3] );
|
|
|
|
length += sprintf( ptr+length, "Status Word:\n" );
|
|
for ( i = 0; statusWordFlags[i].name[0]; i++ ) {
|
|
ptr += sprintf( ptr+length, " %-30s = %s\n", statusWordFlags[i].name, ( stat & ( 1 << statusWordFlags[i].bit ) ) ? "true" : "false" );
|
|
}
|
|
length += sprintf( ptr+length, " %-30s = %d%d%d%d\n", "Condition code", (stat>>8)&1, (stat>>9)&1, (stat>>10)&1, (stat>>14)&1 );
|
|
length += sprintf( ptr+length, " %-30s = %d\n", "Top of stack pointer", (stat>>11)&7 );
|
|
|
|
return length;
|
|
}
|
|
|
|
/*
|
|
===============
|
|
Sys_FPU_StackIsEmpty
|
|
===============
|
|
*/
|
|
bool Sys_FPU_StackIsEmpty() {
|
|
__asm {
|
|
mov eax, statePtr
|
|
fnstenv [eax]
|
|
mov eax, [eax+8]
|
|
xor eax, 0xFFFFFFFF
|
|
and eax, 0x0000FFFF
|
|
jz empty
|
|
}
|
|
return false;
|
|
empty:
|
|
return true;
|
|
}
|
|
|
|
/*
|
|
===============
|
|
Sys_FPU_ClearStack
|
|
===============
|
|
*/
|
|
void Sys_FPU_ClearStack() {
|
|
__asm {
|
|
mov eax, statePtr
|
|
fnstenv [eax]
|
|
mov eax, [eax+8]
|
|
xor eax, 0xFFFFFFFF
|
|
mov edx, (3<<14)
|
|
emptyStack:
|
|
mov ecx, eax
|
|
and ecx, edx
|
|
jz done
|
|
fstp st
|
|
shr edx, 2
|
|
jmp emptyStack
|
|
done:
|
|
}
|
|
}
|
|
|
|
/*
|
|
===============
|
|
Sys_FPU_GetState
|
|
|
|
gets the FPU state without changing the state
|
|
===============
|
|
*/
|
|
const char *Sys_FPU_GetState() {
|
|
double fpuStack[8] = { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 };
|
|
double *fpuStackPtr = fpuStack;
|
|
int i, numValues;
|
|
char *ptr;
|
|
|
|
__asm {
|
|
mov esi, statePtr
|
|
mov edi, fpuStackPtr
|
|
fnstenv [esi]
|
|
mov esi, [esi+8]
|
|
xor esi, 0xFFFFFFFF
|
|
mov edx, (3<<14)
|
|
xor eax, eax
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fst qword ptr [edi+0]
|
|
inc eax
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(1)
|
|
fst qword ptr [edi+8]
|
|
inc eax
|
|
fxch st(1)
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(2)
|
|
fst qword ptr [edi+16]
|
|
inc eax
|
|
fxch st(2)
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(3)
|
|
fst qword ptr [edi+24]
|
|
inc eax
|
|
fxch st(3)
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(4)
|
|
fst qword ptr [edi+32]
|
|
inc eax
|
|
fxch st(4)
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(5)
|
|
fst qword ptr [edi+40]
|
|
inc eax
|
|
fxch st(5)
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(6)
|
|
fst qword ptr [edi+48]
|
|
inc eax
|
|
fxch st(6)
|
|
shr edx, 2
|
|
mov ecx, esi
|
|
and ecx, edx
|
|
jz done
|
|
fxch st(7)
|
|
fst qword ptr [edi+56]
|
|
inc eax
|
|
fxch st(7)
|
|
done:
|
|
mov numValues, eax
|
|
}
|
|
|
|
int ctrl = *(int *)&fpuState[0];
|
|
int stat = *(int *)&fpuState[4];
|
|
int tags = *(int *)&fpuState[8];
|
|
int inof = *(int *)&fpuState[12];
|
|
int inse = *(int *)&fpuState[16];
|
|
int opof = *(int *)&fpuState[20];
|
|
int opse = *(int *)&fpuState[24];
|
|
|
|
ptr = fpuString;
|
|
ptr += sprintf( ptr,"FPU State:\n"
|
|
"num values on stack = %d\n", numValues );
|
|
for ( i = 0; i < 8; i++ ) {
|
|
ptr += sprintf( ptr, "ST%d = %1.10e\n", i, fpuStack[i] );
|
|
}
|
|
|
|
Sys_FPU_PrintStateFlags( ptr, ctrl, stat, tags, inof, inse, opof, opse );
|
|
|
|
return fpuString;
|
|
}
|
|
|
|
/*
|
|
===============
|
|
Sys_FPU_EnableExceptions
|
|
===============
|
|
*/
|
|
void Sys_FPU_EnableExceptions( int exceptions ) {
|
|
__asm {
|
|
mov eax, statePtr
|
|
mov ecx, exceptions
|
|
and cx, 63
|
|
not cx
|
|
fnstcw word ptr [eax]
|
|
mov bx, word ptr [eax]
|
|
or bx, 63
|
|
and bx, cx
|
|
mov word ptr [eax], bx
|
|
fldcw word ptr [eax]
|
|
}
|
|
}
|
|
|
|
/*
|
|
===============
|
|
Sys_FPU_SetPrecision
|
|
===============
|
|
*/
|
|
void Sys_FPU_SetPrecision( int precision ) {
|
|
short precisionBitTable[4] = { 0, 1, 3, 0 };
|
|
short precisionBits = precisionBitTable[precision & 3] << 8;
|
|
short precisionMask = ~( ( 1 << 9 ) | ( 1 << 8 ) );
|
|
|
|
__asm {
|
|
mov eax, statePtr
|
|
mov cx, precisionBits
|
|
fnstcw word ptr [eax]
|
|
mov bx, word ptr [eax]
|
|
and bx, precisionMask
|
|
or bx, cx
|
|
mov word ptr [eax], bx
|
|
fldcw word ptr [eax]
|
|
}
|
|
}
|
|
|
|
/*
|
|
================
|
|
Sys_FPU_SetRounding
|
|
================
|
|
*/
|
|
void Sys_FPU_SetRounding( int rounding ) {
|
|
short roundingBitTable[4] = { 0, 1, 2, 3 };
|
|
short roundingBits = roundingBitTable[rounding & 3] << 10;
|
|
short roundingMask = ~( ( 1 << 11 ) | ( 1 << 10 ) );
|
|
|
|
__asm {
|
|
mov eax, statePtr
|
|
mov cx, roundingBits
|
|
fnstcw word ptr [eax]
|
|
mov bx, word ptr [eax]
|
|
and bx, roundingMask
|
|
or bx, cx
|
|
mov word ptr [eax], bx
|
|
fldcw word ptr [eax]
|
|
}
|
|
}
|
|
|
|
/*
|
|
================
|
|
Sys_FPU_SetDAZ
|
|
================
|
|
*/
|
|
void Sys_FPU_SetDAZ( bool enable ) {
|
|
DWORD dwData;
|
|
|
|
_asm {
|
|
movzx ecx, byte ptr enable
|
|
and ecx, 1
|
|
shl ecx, 6
|
|
STMXCSR dword ptr dwData
|
|
mov eax, dwData
|
|
and eax, ~(1<<6) // clear DAX bit
|
|
or eax, ecx // set the DAZ bit
|
|
mov dwData, eax
|
|
LDMXCSR dword ptr dwData
|
|
}
|
|
}
|
|
|
|
/*
|
|
================
|
|
Sys_FPU_SetFTZ
|
|
================
|
|
*/
|
|
void Sys_FPU_SetFTZ( bool enable ) {
|
|
DWORD dwData;
|
|
|
|
_asm {
|
|
movzx ecx, byte ptr enable
|
|
and ecx, 1
|
|
shl ecx, 15
|
|
STMXCSR dword ptr dwData
|
|
mov eax, dwData
|
|
and eax, ~(1<<15) // clear FTZ bit
|
|
or eax, ecx // set the FTZ bit
|
|
mov dwData, eax
|
|
LDMXCSR dword ptr dwData
|
|
}
|
|
}
|