mirror of
https://github.com/ZDoom/qzdoom.git
synced 2024-11-29 15:32:54 +00:00
db86385cf6
The only reason this even existed was that ZDoom's original VC projects used __fastcall. The CMake generated project do not, they stick to __cdecl. Since no performance gain can be seen by using __fastcall the best course of action is to just remove all traces of it from the source and forget that it ever existed.
368 lines
9.3 KiB
C++
368 lines
9.3 KiB
C++
#include "doomtype.h"
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#include "doomdef.h"
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#include "x86.h"
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extern "C"
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{
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CPUInfo CPU;
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}
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#if !defined(__amd64__) && !defined(__i386__) && !defined(_M_IX86) && !defined(_M_X64)
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void CheckCPUID(CPUInfo *cpu)
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{
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memset(cpu, 0, sizeof(*cpu));
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cpu->DataL1LineSize = 32; // Assume a 32-byte cache line
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}
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void DumpCPUInfo(const CPUInfo *cpu)
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{
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}
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#else
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#ifdef _MSC_VER
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#include <intrin.h>
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#endif
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#include <mmintrin.h>
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#include <emmintrin.h>
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#ifdef __GNUC__
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#if defined(__i386__) && defined(__PIC__)
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// %ebx may by the PIC register. */
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#define __cpuid(output, func) \
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__asm__ __volatile__("xchgl\t%%ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %1\n\t" \
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: "=a" ((output)[0]), "=r" ((output)[1]), "=c" ((output)[2]), "=d" ((output)[3]) \
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: "a" (func));
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#else
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#define __cpuid(output, func) __asm__ __volatile__("cpuid" : "=a" ((output)[0]),\
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"=b" ((output)[1]), "=c" ((output)[2]), "=d" ((output)[3]) : "a" (func));
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#endif
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#endif
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void CheckCPUID(CPUInfo *cpu)
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{
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int foo[4];
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unsigned int maxext;
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memset(cpu, 0, sizeof(*cpu));
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cpu->DataL1LineSize = 32; // Assume a 32-byte cache line
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#if !defined(_M_IX86) && !defined(__i386__) && !defined(_M_X64) && !defined(__amd64__)
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return;
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#else
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#if defined(_M_IX86) || defined(__i386__)
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// Old 486s do not have CPUID, so we must test for its presence.
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// This code is adapted from the samples in AMD's document
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// entitled "AMD-K6 MMX Processor Multimedia Extensions."
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#ifndef __GNUC__
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__asm
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{
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pushfd // save EFLAGS
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pop eax // store EFLAGS in EAX
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mov ecx,eax // save in ECX for later testing
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xor eax,0x00200000 // toggle bit 21
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push eax // put to stack
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popfd // save changed EAX to EFLAGS
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pushfd // push EFLAGS to TOS
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pop eax // store EFLAGS in EAX
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cmp eax,ecx // see if bit 21 has changed
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jne haveid // if no change, then no CPUID
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}
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return;
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haveid:
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#else
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int oldfd, newfd;
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__asm__ __volatile__("\t"
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"pushf\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl $0x200000,%0\n\t"
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"pushl %0\n\t"
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"popf\n\t"
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"pushf\n\t"
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"popl %0\n\t"
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: "=r" (newfd), "=r" (oldfd));
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if (oldfd == newfd)
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{
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return;
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}
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#endif
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#endif
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// Get vendor ID
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__cpuid(foo, 0);
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cpu->dwVendorID[0] = foo[1];
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cpu->dwVendorID[1] = foo[3];
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cpu->dwVendorID[2] = foo[2];
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if (foo[1] == MAKE_ID('A','u','t','h') &&
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foo[3] == MAKE_ID('e','n','t','i') &&
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foo[2] == MAKE_ID('c','A','M','D'))
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{
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cpu->bIsAMD = true;
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}
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// Get features flags and other info
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__cpuid(foo, 1);
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cpu->FeatureFlags[0] = foo[1]; // Store brand index and other stuff
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cpu->FeatureFlags[1] = foo[2]; // Store extended feature flags
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cpu->FeatureFlags[2] = foo[3]; // Store feature flags
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// If CLFLUSH instruction is supported, get the real cache line size.
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if (foo[3] & (1 << 19))
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{
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cpu->DataL1LineSize = (foo[1] & 0xFF00) >> (8 - 3);
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}
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cpu->Stepping = foo[0] & 0x0F;
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cpu->Type = (foo[0] & 0x3000) >> 12; // valid on Intel only
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cpu->Model = (foo[0] & 0xF0) >> 4;
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cpu->Family = (foo[0] & 0xF00) >> 8;
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if (cpu->Family == 15)
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{ // Add extended family.
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cpu->Family += (foo[0] >> 20) & 0xFF;
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}
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if (cpu->Family == 6 || cpu->Family == 15)
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{ // Add extended model ID.
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cpu->Model |= (foo[0] >> 12) & 0xF0;
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}
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// Check for extended functions.
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__cpuid(foo, 0x80000000);
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maxext = (unsigned int)foo[0];
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if (maxext >= 0x80000004)
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{ // Get processor brand string.
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__cpuid((int *)&cpu->dwCPUString[0], 0x80000002);
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__cpuid((int *)&cpu->dwCPUString[4], 0x80000003);
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__cpuid((int *)&cpu->dwCPUString[8], 0x80000004);
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}
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if (cpu->bIsAMD)
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{
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if (maxext >= 0x80000005)
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{ // Get data L1 cache info.
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__cpuid(foo, 0x80000005);
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cpu->AMD_DataL1Info = foo[2];
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}
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if (maxext >= 0x80000001)
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{ // Get AMD-specific feature flags.
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__cpuid(foo, 0x80000001);
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cpu->AMDStepping = foo[0] & 0x0F;
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cpu->AMDModel = (foo[0] & 0xF0) >> 4;
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cpu->AMDFamily = (foo[0] & 0xF00) >> 8;
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if (cpu->AMDFamily == 15)
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{ // Add extended model and family.
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cpu->AMDFamily += (foo[0] >> 20) & 0xFF;
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cpu->AMDModel |= (foo[0] >> 12) & 0xF0;
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}
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cpu->FeatureFlags[3] = foo[3]; // AMD feature flags
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}
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}
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#endif
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}
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void DumpCPUInfo(const CPUInfo *cpu)
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{
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char cpustring[4*4*3+1];
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// Why does Intel right-justify this string (on P4s)
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// or add extra spaces (on Cores)?
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const char *f = cpu->CPUString;
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char *t;
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// Skip extra whitespace at the beginning.
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while (*f == ' ')
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{
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++f;
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}
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// Copy string to temp buffer, but condense consecutive
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// spaces to a single space character.
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for (t = cpustring; *f != '\0'; ++f)
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{
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if (*f == ' ' && *(f - 1) == ' ')
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{
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continue;
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}
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*t++ = *f;
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}
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*t = '\0';
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if (cpu->VendorID[0] && !batchrun)
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{
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Printf("CPU Vendor ID: %s\n", cpu->VendorID);
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if (cpustring[0])
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{
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Printf(" Name: %s\n", cpustring);
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}
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if (cpu->bIsAMD)
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{
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Printf(" Family %d (%d), Model %d, Stepping %d\n",
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cpu->Family, cpu->AMDFamily, cpu->AMDModel, cpu->AMDStepping);
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}
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else
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{
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Printf(" Family %d, Model %d, Stepping %d\n",
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cpu->Family, cpu->Model, cpu->Stepping);
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}
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Printf(" Features:");
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if (cpu->bMMX) Printf(" MMX");
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if (cpu->bMMXPlus) Printf(" MMX+");
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if (cpu->bSSE) Printf(" SSE");
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if (cpu->bSSE2) Printf(" SSE2");
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if (cpu->bSSE3) Printf(" SSE3");
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if (cpu->bSSSE3) Printf(" SSSE3");
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if (cpu->bSSE41) Printf(" SSE4.1");
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if (cpu->bSSE42) Printf(" SSE4.2");
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if (cpu->b3DNow) Printf(" 3DNow!");
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if (cpu->b3DNowPlus) Printf(" 3DNow!+");
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Printf ("\n");
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}
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}
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#if 0
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// Compiler output for this function is crap compared to the assembly
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// version, which is why it isn't used.
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void DoBlending_MMX2(const PalEntry *from, PalEntry *to, int count, int r, int g, int b, int a)
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{
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__m64 blendcolor;
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__m64 blendalpha;
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__m64 zero;
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__m64 blending256;
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__m64 color1;
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__m64 color2;
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zero = _mm_setzero_si64();
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#ifndef __GNUC__
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blending256.m64_i64 = 0x10001000100;
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#else
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blending256 = (__m64)0x10001000100ll;
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#endif
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blendcolor = _mm_unpacklo_pi8(_m_from_int((r << 16) | (g << 8) | b), zero); // 000000RR 00GG00BB
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blendalpha = _mm_unpacklo_pi8(_m_from_int((a << 16) | (a << 8) | a), zero); // 000000AA 00AA00AA
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blendcolor = _mm_mullo_pi16(blendcolor, blendalpha); // premultiply blend by alpha
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blendalpha = _mm_subs_pu16(blending256, blendalpha); // one minus alpha
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// Do two colors per iteration: Count must be even
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for (count >>= 1; count > 0; --count)
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{
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color1 = *(__m64 *)from; // 00r2g2b2 00r1g1b1
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from += 2;
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color2 = _mm_unpackhi_pi8(color1, zero); // 000000r2 00g200b2
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color1 = _mm_unpacklo_pi8(color1, zero); // 000000r1 00g100b1
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color1 = _mm_mullo_pi16(blendalpha, color1); // 0000r1rr g1ggb1bb
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color2 = _mm_mullo_pi16(blendalpha, color2); // 0000r2rr g2ggb2bb
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color1 = _mm_adds_pu16(blendcolor, color1);
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color2 = _mm_adds_pu16(blendcolor, color2);
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color1 = _mm_srli_pi16(color1, 8);
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color2 = _mm_srli_pi16(color2, 8);
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*(__m64 *)to = _mm_packs_pu16(color1, color2); // 00r2g2b2 00r1g1b1
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to += 2;
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}
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_mm_empty();
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}
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#endif
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#ifdef X86_ASM
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extern "C" void DoBlending_MMX(const PalEntry *from, PalEntry *to, int count, int r, int g, int b, int a);
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#endif
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void DoBlending_SSE2(const PalEntry *from, PalEntry *to, int count, int r, int g, int b, int a)
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{
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__m128i blendcolor;
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__m128i blendalpha;
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__m128i zero;
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__m128i blending256;
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__m128i color1;
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__m128i color2;
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size_t unaligned;
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unaligned = ((size_t)from | (size_t)to) & 0xF;
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#ifdef X86_ASM
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// For unaligned accesses, the assembly MMX version is slightly faster.
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// Note that using unaligned SSE loads and stores is still faster than
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// the compiler-generated MMX version.
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if (unaligned)
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{
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DoBlending_MMX(from, to, count, r, g, b, a);
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return;
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}
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#endif
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#if defined(__amd64__) || defined(_M_X64)
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long long color;
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blending256 = _mm_set_epi64x(0x10001000100ll, 0x10001000100ll);
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color = ((long long)r << 32) | (g << 16) | b;
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blendcolor = _mm_set_epi64x(color, color);
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color = ((long long)a << 32) | (a << 16) | a;
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blendalpha = _mm_set_epi64x(color, color);
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#else
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int color;
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blending256 = _mm_set_epi32(0x100, 0x1000100, 0x100, 0x1000100);
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color = (g << 16) | b;
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blendcolor = _mm_set_epi32(r, color, r, color);
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color = (a << 16) | a;
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blendalpha = _mm_set_epi32(a, color, a, color);
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#endif
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blendcolor = _mm_mullo_epi16(blendcolor, blendalpha); // premultiply blend by alpha
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blendalpha = _mm_subs_epu16(blending256, blendalpha); // one minus alpha
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zero = _mm_setzero_si128();
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#ifndef X86_ASM
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if (unaligned)
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{
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for (count >>= 2; count > 0; --count)
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{
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color1 = _mm_loadu_si128((__m128i *)from);
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from += 4;
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color2 = _mm_unpackhi_epi8(color1, zero);
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color1 = _mm_unpacklo_epi8(color1, zero);
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color1 = _mm_mullo_epi16(blendalpha, color1);
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color2 = _mm_mullo_epi16(blendalpha, color2);
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color1 = _mm_adds_epu16(blendcolor, color1);
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color2 = _mm_adds_epu16(blendcolor, color2);
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color1 = _mm_srli_epi16(color1, 8);
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color2 = _mm_srli_epi16(color2, 8);
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_mm_storeu_si128((__m128i *)to, _mm_packus_epi16(color1, color2));
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to += 4;
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}
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}
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else
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#endif
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{
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for (count >>= 2; count > 0; --count)
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{
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color1 = _mm_load_si128((__m128i *)from);
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from += 4;
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color2 = _mm_unpackhi_epi8(color1, zero);
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color1 = _mm_unpacklo_epi8(color1, zero);
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color1 = _mm_mullo_epi16(blendalpha, color1);
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color2 = _mm_mullo_epi16(blendalpha, color2);
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color1 = _mm_adds_epu16(blendcolor, color1);
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color2 = _mm_adds_epu16(blendcolor, color2);
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color1 = _mm_srli_epi16(color1, 8);
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color2 = _mm_srli_epi16(color2, 8);
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_mm_store_si128((__m128i *)to, _mm_packus_epi16(color1, color2));
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to += 4;
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}
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}
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}
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#endif
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