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- Move the RET and RETI final flag into the high bit of the destination selector.
SVN r3922 (scripting)
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parent
35ba5b79d3
commit
c2e700f116
5 changed files with 35 additions and 27 deletions
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@ -3995,7 +3995,7 @@ ExpEmit FxDamageValue::Emit(VMFunctionBuilder *build)
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assert(emitval.RegType == REGT_INT);
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build->Emit(OP_RET, 0, REGT_INT | (emitval.Konst ? REGT_KONST : 0), emitval.RegNum);
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}
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build->Emit(OP_RETI, 1, 0x8000 | (int)Calculated);
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build->Emit(OP_RETI, 1 | RET_FINAL, Calculated);
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return ExpEmit();
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}
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@ -119,12 +119,14 @@ enum
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REGT_KONST = 4,
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REGT_MULTIREG = 8, // (e.g. a vector)
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REGT_FINAL = 16, // used with RET: this is the final return value
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REGT_ADDROF = 32, // used with PARAM: pass address of this register
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REGT_NIL = 255 // parameter was omitted
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};
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#define RET_FINAL (0x80) // Used with RET and RETI in the destination slot: this is the final return value
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// Tags for address registers
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enum
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{
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@ -501,13 +501,14 @@ size_t VMFunctionBuilder::EmitLoadInt(int regnum, int value)
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size_t VMFunctionBuilder::EmitRetInt(int retnum, bool final, int value)
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{
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if (value >= -16384 && value <= 16383)
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assert(retnum >= 0 && retnum <= 127);
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if (value >= -32768 && value <= 32767)
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{
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return Emit(OP_RETI, retnum, value | (final << 15));
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return Emit(OP_RETI, retnum | (final << 7), value);
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}
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else
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{
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return Emit(OP_RETI, retnum, REGT_INT | REGT_KONST | (final ? REGT_FINAL : 0), GetConstantInt(value));
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return Emit(OP_RET, retnum | (final << 7), REGT_INT | REGT_KONST, GetConstantInt(value));
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}
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}
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@ -231,15 +231,15 @@ void VMDisasm(FILE *out, const VMOP *code, int codesize, const VMScriptFunction
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case OP_RET:
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if (code[i].b != REGT_NIL)
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{
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if ((code[i].b & REGT_FINAL) && a == 0)
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if (a == RET_FINAL)
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{
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col = print_reg(out, 0, code[i].i16u, MODE_PARAM, 16, func);
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}
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else
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{
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col = print_reg(out, 0, a, (mode & MODE_ATYPE) >> MODE_ASHIFT, 24, func);
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col = print_reg(out, 0, a & ~RET_FINAL, (mode & MODE_ATYPE) >> MODE_ASHIFT, 24, func);
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col += print_reg(out, col, code[i].i16u, MODE_PARAM, 16, func);
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if (code[i].b & REGT_FINAL)
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if (a & RET_FINAL)
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{
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col += printf_wrapper(out, " [final]");
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}
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@ -248,15 +248,15 @@ void VMDisasm(FILE *out, const VMOP *code, int codesize, const VMScriptFunction
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break;
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case OP_RETI:
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if (a == 0 && code[i].i16 & 0x8000)
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if (a == RET_FINAL)
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{
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col = printf_wrapper(out, "%d", (code[i].i16 << 17) >> 17);
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col = printf_wrapper(out, "%d", code[i].i16);
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}
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else
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{
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col = print_reg(out, 0, a, (mode & MODE_ATYPE) >> MODE_ASHIFT, 24, func);
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col += print_reg(out, col, (code[i].i16 << 17) >> 17, MODE_IMMS, 16, func);
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if (code[i].i16 & 0x8000)
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col = print_reg(out, 0, a & ~RET_FINAL, (mode & MODE_ATYPE) >> MODE_ASHIFT, 24, func);
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col += print_reg(out, col, code[i].i16, MODE_IMMS, 16, func);
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if (a & RET_FINAL)
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{
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col += printf_wrapper(out, " [final]");
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}
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@ -584,25 +584,30 @@ begin:
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return 0;
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}
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assert(ret != NULL || numret == 0);
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if (a < numret)
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{
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SetReturn(reg, f, &ret[a], B, C);
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}
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if (B & REGT_FINAL)
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{
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return a < numret ? a + 1 : numret;
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int retnum = a & ~RET_FINAL;
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if (retnum < numret)
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{
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SetReturn(reg, f, &ret[retnum], B, C);
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}
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if (a & RET_FINAL)
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{
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return retnum < numret ? retnum + 1 : numret;
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}
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}
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NEXTOP;
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OP(RETI):
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assert(ret != NULL || numret == 0);
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if (a < numret)
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{
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// Shifting by 17 to wipe out the final bit
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ret[a].SetInt(((pc[-1].i16) << 17) >> 17);
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}
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if (pc[-1].i16 & 0x8000)
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{
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return a < numret ? a + 1 : numret;
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int retnum = a & ~RET_FINAL;
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if (retnum < numret)
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{
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ret[retnum].SetInt(BCs);
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}
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if (a & RET_FINAL)
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{
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return retnum < numret ? retnum + 1 : numret;
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}
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}
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NEXTOP;
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OP(RESULT):
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@ -1490,7 +1495,7 @@ static void SetReturn(const VMRegisters ®, VMFrame *frame, VMReturn *ret, VM_
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VMScriptFunction *func = static_cast<VMScriptFunction *>(frame->Func);
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assert(func != NULL && !func->Native);
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assert((regtype & ~(REGT_KONST | REGT_FINAL)) == ret->RegType);
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assert((regtype & ~REGT_KONST) == ret->RegType);
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switch (regtype & REGT_TYPE)
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{
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