mirror of
https://github.com/ZDoom/qzdoom-gpl.git
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dda5ddd3c2
registers AMD64 provides, this routine still needs to be written as self- modifying code for maximum performance. The additional registers do allow for further optimization over the x86 version by allowing all four pixels to be in flight at the same time. The end result is that AMD64 ASM is about 2.18 times faster than AMD64 C and about 1.06 times faster than x86 ASM. (For further comparison, AMD64 C and x86 C are practically the same for this function.) Should I port any more assembly to AMD64, mvlineasm4 is the most likely candidate, but it's not used enough at this point to bother. Also, this may or may not work with Linux at the moment, since it doesn't have the eh_handler metadata. Win64 is easier, since I just need to structure the function prologue and epilogue properly and use some assembler directives/macros to automatically generate the metadata. And that brings up another point: You need YASM to assemble the AMD64 code, because NASM doesn't support the Win64 metadata directives. - Added an SSE version of DoBlending. This is strictly C intrinsics. VC++ still throws around unneccessary register moves. GCC seems to be pretty close to optimal, requiring only about 2 cycles/color. They're both faster than my hand-written MMX routine, so I don't need to feel bad about not hand-optimizing this for x64 builds. - Removed an extra instruction from DoBlending_MMX, transposed two instructions, and unrolled it once, shaving off about 80 cycles from the time required to blend 256 palette entries. Why? Because I tried writing a C version of the routine using compiler intrinsics and was appalled by all the extra movq's VC++ added to the code. GCC was better, but still generated extra instructions. I only wanted a C version because I can't use inline assembly with VC++'s x64 compiler, and x64 assembly is a bit of a pain. (It's a pain because Linux and Windows have different calling conventions, and you need to maintain extra metadata for functions.) So, the assembly version stays and the C version stays out. - Removed all the pixel doubling r_detail modes, since the one platform they were intended to assist (486) actually sees very little benefit from them. - Rewrote CheckMMX in C and renamed it to CheckCPU. - Fixed: CPUID function 0x80000005 is specified to return detailed L1 cache only for AMD processors, so we must not use it on other architectures, or we end up overwriting the L1 cache line size with 0 or some other number we don't actually understand. SVN r1134 (trunk)
333 lines
6.9 KiB
NASM
333 lines
6.9 KiB
NASM
%include "valgrind.inc"
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%ifdef M_TARGET_WATCOM
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SEGMENT DATA PUBLIC ALIGN=16 CLASS=DATA USE32
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SEGMENT DATA
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%else
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SECTION .data
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%endif
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%ifndef M_TARGET_LINUX
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%define ylookup _ylookup
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%define vplce _vplce
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%define vince _vince
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%define palookupoffse _palookupoffse
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%define bufplce _bufplce
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%define dc_iscale _dc_iscale
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%define dc_colormap _dc_colormap
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%define dc_count _dc_count
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%define dc_dest _dc_dest
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%define dc_source _dc_source
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%define dc_texturefrac _dc_texturefrac
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%define dc_pitch _dc_pitch
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%define setupvlinetallasm _setupvlinetallasm
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%define vlinetallasm4 _vlinetallasm4
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%define vlinetallasmathlon4 _vlinetallasmathlon4
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%define vlinetallasm1 _vlinetallasm1
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%define prevlinetallasm1 _prevlinetallasm1
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%endif
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EXTERN vplce
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EXTERN vince
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EXTERN palookupoffse
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EXTERN bufplce
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EXTERN ylookup
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EXTERN dc_iscale
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EXTERN dc_colormap
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EXTERN dc_count
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EXTERN dc_dest
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EXTERN dc_source
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EXTERN dc_texturefrac
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EXTERN dc_pitch
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GLOBAL vlt4pitch
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GLOBAL vlt1pitch
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%ifdef M_TARGET_WATCOM
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SEGMENT CODE PUBLIC ALIGN=16 CLASS=CODE USE32
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SEGMENT CODE
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%else
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SECTION .text
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%endif
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ALIGN 16
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GLOBAL setpitch3
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setpitch3:
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mov [vltpitch+2], eax
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mov [vltpitcha+2],eax
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mov [vlt1pitch1+2], eax
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mov [vlt1pitch2+2], eax
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selfmod vltpitch, vlt1pitch2+6
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ret
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ALIGN 16
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GLOBAL setupvlinetallasm
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setupvlinetallasm:
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mov ecx, [esp+4]
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mov [shifter1+2], cl
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mov [shifter2+2], cl
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mov [shifter3+2], cl
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mov [shifter4+2], cl
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mov [shifter1a+2], cl
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mov [shifter2a+2], cl
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mov [shifter3a+2], cl
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mov [shifter4a+2], cl
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mov [preshift+2], cl
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mov [shift11+2], cl
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mov [shift12+2], cl
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selfmod shifter1, shift12+6
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ret
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SECTION .rtext progbits alloc exec write align=64
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ALIGN 16
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GLOBAL vlinetallasm4
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vlinetallasm4:
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push ebx
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mov eax, [bufplce+0]
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mov ebx, [bufplce+4]
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mov ecx, [bufplce+8]
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mov edx, [bufplce+12]
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mov [source1+3], eax
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mov [source2+3], ebx
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mov [source3+3], ecx
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mov [source4+3], edx
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mov eax, [palookupoffse+0]
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mov ebx, [palookupoffse+4]
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mov ecx, [palookupoffse+8]
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mov edx, [palookupoffse+12]
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mov [lookup1+2], eax
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mov [lookup2+2], ebx
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mov [lookup3+2], ecx
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mov [lookup4+2], edx
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mov eax, [vince+0]
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mov ebx, [vince+4]
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mov ecx, [vince+8]
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mov edx, [vince+12]
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mov [step1+2], eax
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mov [step2+2], ebx
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mov [step3+2], ecx
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mov [step4+1], edx
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push ebp
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push esi
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push edi
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mov ecx, [dc_count]
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mov edi, [dc_dest]
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mov eax, dword [ylookup+ecx*4-4]
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add eax, edi
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sub edi, eax
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mov [write1+2],eax
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inc eax
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mov [write2+2],eax
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inc eax
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mov [write3+2],eax
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inc eax
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mov [write4+2],eax
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mov ebx, [vplce]
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mov ecx, [vplce+4]
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mov esi, [vplce+8]
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mov eax, [vplce+12]
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selfmod loopit, vltpitch
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jmp loopit
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ALIGN 16
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loopit:
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mov edx, ebx
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shifter1: shr edx, 24
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source1: movzx edx, BYTE [edx+0x88888888]
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lookup1: mov dl, [edx+0x88888888]
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write1: mov [edi+0x88888880], dl
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step1: add ebx, 0x88888888
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mov edx, ecx
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shifter2: shr edx, 24
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source2: movzx edx, BYTE [edx+0x88888888]
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lookup2: mov dl, [edx+0x88888888]
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write2: mov [edi+0x88888881], dl
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step2: add ecx, 0x88888888
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mov edx, esi
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shifter3: shr edx, 24
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source3: movzx edx, BYTE [edx+0x88888888]
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lookup3: mov dl, BYTE [edx+0x88888888]
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write3: mov [edi+0x88888882], dl
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step3: add esi, 0x88888888
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mov edx, eax
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shifter4: shr edx, 24
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source4: movzx edx, BYTE [edx+0x88888888]
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lookup4: mov dl, [edx+0x88888888]
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write4: mov [edi+0x88888883], dl
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step4: add eax, 0x88888888
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vltpitch: add edi, 320
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jle near loopit
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mov [vplce], ebx
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mov [vplce+4], ecx
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mov [vplce+8], esi
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mov [vplce+12], eax
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pop edi
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pop esi
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pop ebp
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pop ebx
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ret
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ALIGN 16
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GLOBAL vlinetallasmathlon4
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vlinetallasmathlon4:
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push ebx
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mov eax, [bufplce+0]
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mov ebx, [bufplce+4]
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mov ecx, [bufplce+8]
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mov edx, [bufplce+12]
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mov [source1a+3], eax
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mov [source2a+3], ebx
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mov [source3a+3], ecx
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mov [source4a+3], edx
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mov eax, [palookupoffse+0]
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mov ebx, [palookupoffse+4]
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mov ecx, [palookupoffse+8]
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mov edx, [palookupoffse+12]
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mov [lookup1a+2], eax
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mov [lookup2a+2], ebx
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mov [lookup3a+2], ecx
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mov [lookup4a+2], edx
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mov eax, [vince+0]
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mov ebx, [vince+4]
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mov ecx, [vince+8]
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mov edx, [vince+12]
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mov [step1a+2], eax
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mov [step2a+2], ebx
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mov [step3a+2], ecx
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mov [step4a+1], edx
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push ebp
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push esi
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push edi
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mov ecx, [dc_count]
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mov edi, [dc_dest]
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mov eax, dword [ylookup+ecx*4-4]
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add eax, edi
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sub edi, eax
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mov [write1a+2],eax
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inc eax
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mov [write2a+2],eax
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inc eax
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mov [write3a+2],eax
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inc eax
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mov [write4a+2],eax
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mov ebp, [vplce]
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mov ecx, [vplce+4]
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mov esi, [vplce+8]
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mov eax, [vplce+12]
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selfmod loopita, vltpitcha
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jmp loopita
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; Unfortunately, this code has not been carefully analyzed to determine
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; how well it utilizes the processor's instruction units. Instead, I just
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; kept rearranging code, seeing what sped it up and what slowed it down
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; until I arrived at this. The is the fastest version I was able to
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; manage, but that does not mean it cannot be made faster with careful
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; instructing shuffling.
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ALIGN 64
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loopita: mov edx, ebp
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mov ebx, ecx
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shifter1a: shr edx, 24
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shifter2a: shr ebx, 24
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source1a: movzx edx, BYTE [edx+0x88888888]
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source2a: movzx ebx, BYTE [ebx+0x88888888]
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step1a: add ebp, 0x88888888
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step2a: add ecx, 0x88888888
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lookup1a: mov dl, [edx+0x88888888]
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lookup2a: mov dh, [ebx+0x88888888]
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mov ebx, esi
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write1a: mov [edi+0x88888880], dl
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write2a: mov [edi+0x88888881], dh
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shifter3a: shr ebx, 24
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mov edx, eax
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source3a: movzx ebx, BYTE [ebx+0x88888888]
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shifter4a: shr edx, 24
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step3a: add esi, 0x88888888
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source4a: movzx edx, BYTE [edx+0x88888888]
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step4a: add eax, 0x88888888
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lookup3a: mov bl, [ebx+0x88888888]
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lookup4a: mov dl, [edx+0x88888888]
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write3a: mov [edi+0x88888882], bl
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write4a: mov [edi+0x88888883], dl
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vltpitcha: add edi, 320
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jle near loopita
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mov [vplce], ebp
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mov [vplce+4], ecx
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mov [vplce+8], esi
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mov [vplce+12], eax
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pop edi
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pop esi
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pop ebp
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pop ebx
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ret
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ALIGN 16
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GLOBAL prevlinetallasm1
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prevlinetallasm1:
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mov ecx, [dc_count]
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cmp ecx, 1
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ja vlinetallasm1
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mov eax, [dc_iscale]
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mov edx, [dc_texturefrac]
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add eax, edx
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mov ecx, [dc_source]
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preshift: shr edx, 16
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push ebx
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push edi
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mov edi, [dc_colormap]
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movzx ebx, byte [ecx+edx]
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mov ecx, [dc_dest]
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mov bl, byte [edi+ebx]
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pop edi
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mov byte [ecx], bl
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pop ebx
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ret
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ALIGN 16
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GLOBAL vlinetallasm1
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vlinetallasm1:
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push ebp
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push ebx
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push edi
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push esi
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mov ebp, [dc_count]
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mov ebx, [dc_texturefrac] ; ebx = frac
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mov edi, [dc_dest]
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mov ecx, ebx
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shift11: shr ecx, 16
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mov esi, [dc_source]
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mov edx, [dc_iscale]
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vlt1pitch1: sub edi, 0x88888888
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mov eax, [dc_colormap]
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loop2:
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movzx ecx, BYTE [esi+ecx]
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add ebx, edx
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vlt1pitch2: add edi, 0x88888888
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mov cl,[eax+ecx]
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mov [edi],cl
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mov ecx,ebx
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shift12: shr ecx,16
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dec ebp
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jnz loop2
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mov eax,ebx
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pop esi
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pop edi
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pop ebx
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pop ebp
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ret
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