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823 lines
21 KiB
C
823 lines
21 KiB
C
/* CpuArch.c -- CPU specific code
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2023-05-18 : Igor Pavlov : Public domain */
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#include "Precomp.h"
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// #include <stdio.h>
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#include "CpuArch.h"
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#ifdef MY_CPU_X86_OR_AMD64
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#undef NEED_CHECK_FOR_CPUID
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#if !defined(MY_CPU_AMD64)
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#define NEED_CHECK_FOR_CPUID
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#endif
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/*
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cpuid instruction supports (subFunction) parameter in ECX,
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that is used only with some specific (function) parameter values.
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But we always use only (subFunction==0).
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*/
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/*
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__cpuid(): MSVC and GCC/CLANG use same function/macro name
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but parameters are different.
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We use MSVC __cpuid() parameters style for our z7_x86_cpuid() function.
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*/
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#if defined(__GNUC__) /* && (__GNUC__ >= 10) */ \
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|| defined(__clang__) /* && (__clang_major__ >= 10) */
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/* there was some CLANG/GCC compilers that have issues with
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rbx(ebx) handling in asm blocks in -fPIC mode (__PIC__ is defined).
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compiler's <cpuid.h> contains the macro __cpuid() that is similar to our code.
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The history of __cpuid() changes in CLANG/GCC:
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GCC:
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2007: it preserved ebx for (__PIC__ && __i386__)
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2013: it preserved rbx and ebx for __PIC__
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2014: it doesn't preserves rbx and ebx anymore
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we suppose that (__GNUC__ >= 5) fixed that __PIC__ ebx/rbx problem.
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CLANG:
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2014+: it preserves rbx, but only for 64-bit code. No __PIC__ check.
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Why CLANG cares about 64-bit mode only, and doesn't care about ebx (in 32-bit)?
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Do we need __PIC__ test for CLANG or we must care about rbx even if
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__PIC__ is not defined?
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*/
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#define ASM_LN "\n"
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#if defined(MY_CPU_AMD64) && defined(__PIC__) \
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&& ((defined (__GNUC__) && (__GNUC__ < 5)) || defined(__clang__))
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#define x86_cpuid_MACRO(p, func) { \
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__asm__ __volatile__ ( \
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ASM_LN "mov %%rbx, %q1" \
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ASM_LN "cpuid" \
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ASM_LN "xchg %%rbx, %q1" \
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: "=a" ((p)[0]), "=&r" ((p)[1]), "=c" ((p)[2]), "=d" ((p)[3]) : "0" (func), "2"(0)); }
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/* "=&r" selects free register. It can select even rbx, if that register is free.
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"=&D" for (RDI) also works, but the code can be larger with "=&D"
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"2"(0) means (subFunction = 0),
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2 is (zero-based) index in the output constraint list "=c" (ECX). */
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#elif defined(MY_CPU_X86) && defined(__PIC__) \
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&& ((defined (__GNUC__) && (__GNUC__ < 5)) || defined(__clang__))
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#define x86_cpuid_MACRO(p, func) { \
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__asm__ __volatile__ ( \
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ASM_LN "mov %%ebx, %k1" \
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ASM_LN "cpuid" \
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ASM_LN "xchg %%ebx, %k1" \
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: "=a" ((p)[0]), "=&r" ((p)[1]), "=c" ((p)[2]), "=d" ((p)[3]) : "0" (func), "2"(0)); }
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#else
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#define x86_cpuid_MACRO(p, func) { \
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__asm__ __volatile__ ( \
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ASM_LN "cpuid" \
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: "=a" ((p)[0]), "=b" ((p)[1]), "=c" ((p)[2]), "=d" ((p)[3]) : "0" (func), "2"(0)); }
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#endif
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void Z7_FASTCALL z7_x86_cpuid(UInt32 p[4], UInt32 func)
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{
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x86_cpuid_MACRO(p, func)
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}
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Z7_NO_INLINE
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UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void)
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{
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#if defined(NEED_CHECK_FOR_CPUID)
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#define EFALGS_CPUID_BIT 21
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UInt32 a;
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__asm__ __volatile__ (
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ASM_LN "pushf"
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ASM_LN "pushf"
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ASM_LN "pop %0"
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// ASM_LN "movl %0, %1"
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// ASM_LN "xorl $0x200000, %0"
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ASM_LN "btc %1, %0"
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ASM_LN "push %0"
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ASM_LN "popf"
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ASM_LN "pushf"
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ASM_LN "pop %0"
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ASM_LN "xorl (%%esp), %0"
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ASM_LN "popf"
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ASM_LN
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: "=&r" (a) // "=a"
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: "i" (EFALGS_CPUID_BIT)
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);
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if ((a & (1 << EFALGS_CPUID_BIT)) == 0)
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return 0;
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#endif
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{
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UInt32 p[4];
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x86_cpuid_MACRO(p, 0)
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return p[0];
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}
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}
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#undef ASM_LN
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#elif !defined(_MSC_VER)
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/*
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// for gcc/clang and other: we can try to use __cpuid macro:
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#include <cpuid.h>
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void Z7_FASTCALL z7_x86_cpuid(UInt32 p[4], UInt32 func)
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{
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__cpuid(func, p[0], p[1], p[2], p[3]);
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}
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UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void)
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{
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return (UInt32)__get_cpuid_max(0, NULL);
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}
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*/
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// for unsupported cpuid:
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void Z7_FASTCALL z7_x86_cpuid(UInt32 p[4], UInt32 func)
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{
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UNUSED_VAR(func)
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p[0] = p[1] = p[2] = p[3] = 0;
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}
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UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void)
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{
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return 0;
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}
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#else // _MSC_VER
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#if !defined(MY_CPU_AMD64)
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UInt32 __declspec(naked) Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void)
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{
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#if defined(NEED_CHECK_FOR_CPUID)
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#define EFALGS_CPUID_BIT 21
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__asm pushfd
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__asm pushfd
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/*
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__asm pop eax
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// __asm mov edx, eax
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__asm btc eax, EFALGS_CPUID_BIT
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__asm push eax
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*/
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__asm btc dword ptr [esp], EFALGS_CPUID_BIT
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__asm popfd
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__asm pushfd
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__asm pop eax
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// __asm xor eax, edx
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__asm xor eax, [esp]
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// __asm push edx
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__asm popfd
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__asm and eax, (1 shl EFALGS_CPUID_BIT)
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__asm jz end_func
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#endif
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__asm push ebx
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__asm xor eax, eax // func
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__asm xor ecx, ecx // subFunction (optional) for (func == 0)
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__asm cpuid
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__asm pop ebx
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#if defined(NEED_CHECK_FOR_CPUID)
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end_func:
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#endif
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__asm ret 0
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}
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void __declspec(naked) Z7_FASTCALL z7_x86_cpuid(UInt32 p[4], UInt32 func)
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{
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UNUSED_VAR(p)
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UNUSED_VAR(func)
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__asm push ebx
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__asm push edi
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__asm mov edi, ecx // p
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__asm mov eax, edx // func
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__asm xor ecx, ecx // subfunction (optional) for (func == 0)
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__asm cpuid
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__asm mov [edi ], eax
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__asm mov [edi + 4], ebx
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__asm mov [edi + 8], ecx
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__asm mov [edi + 12], edx
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__asm pop edi
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__asm pop ebx
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__asm ret 0
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}
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#else // MY_CPU_AMD64
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#if _MSC_VER >= 1600
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#include <intrin.h>
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#define MY_cpuidex __cpuidex
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#else
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/*
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__cpuid (func == (0 or 7)) requires subfunction number in ECX.
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MSDN: The __cpuid intrinsic clears the ECX register before calling the cpuid instruction.
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__cpuid() in new MSVC clears ECX.
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__cpuid() in old MSVC (14.00) x64 doesn't clear ECX
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We still can use __cpuid for low (func) values that don't require ECX,
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but __cpuid() in old MSVC will be incorrect for some func values: (func == 7).
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So here we use the hack for old MSVC to send (subFunction) in ECX register to cpuid instruction,
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where ECX value is first parameter for FASTCALL / NO_INLINE func,
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So the caller of MY_cpuidex_HACK() sets ECX as subFunction, and
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old MSVC for __cpuid() doesn't change ECX and cpuid instruction gets (subFunction) value.
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DON'T remove Z7_NO_INLINE and Z7_FASTCALL for MY_cpuidex_HACK(): !!!
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*/
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static
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Z7_NO_INLINE void Z7_FASTCALL MY_cpuidex_HACK(UInt32 subFunction, UInt32 func, int *CPUInfo)
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{
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UNUSED_VAR(subFunction)
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__cpuid(CPUInfo, func);
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}
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#define MY_cpuidex(info, func, func2) MY_cpuidex_HACK(func2, func, info)
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#pragma message("======== MY_cpuidex_HACK WAS USED ========")
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#endif // _MSC_VER >= 1600
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#if !defined(MY_CPU_AMD64)
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/* inlining for __cpuid() in MSVC x86 (32-bit) produces big ineffective code,
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so we disable inlining here */
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Z7_NO_INLINE
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#endif
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void Z7_FASTCALL z7_x86_cpuid(UInt32 p[4], UInt32 func)
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{
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MY_cpuidex((int *)p, (int)func, 0);
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}
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Z7_NO_INLINE
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UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void)
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{
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int a[4];
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MY_cpuidex(a, 0, 0);
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return a[0];
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}
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#endif // MY_CPU_AMD64
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#endif // _MSC_VER
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#if defined(NEED_CHECK_FOR_CPUID)
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#define CHECK_CPUID_IS_SUPPORTED { if (z7_x86_cpuid_GetMaxFunc() == 0) return 0; }
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#else
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#define CHECK_CPUID_IS_SUPPORTED
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#endif
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#undef NEED_CHECK_FOR_CPUID
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static
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BoolInt x86cpuid_Func_1(UInt32 *p)
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{
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CHECK_CPUID_IS_SUPPORTED
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z7_x86_cpuid(p, 1);
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return True;
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}
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/*
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static const UInt32 kVendors[][1] =
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{
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{ 0x756E6547 }, // , 0x49656E69, 0x6C65746E },
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{ 0x68747541 }, // , 0x69746E65, 0x444D4163 },
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{ 0x746E6543 } // , 0x48727561, 0x736C7561 }
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};
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*/
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/*
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typedef struct
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{
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UInt32 maxFunc;
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UInt32 vendor[3];
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UInt32 ver;
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UInt32 b;
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UInt32 c;
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UInt32 d;
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} Cx86cpuid;
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enum
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{
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CPU_FIRM_INTEL,
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CPU_FIRM_AMD,
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CPU_FIRM_VIA
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};
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int x86cpuid_GetFirm(const Cx86cpuid *p);
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#define x86cpuid_ver_GetFamily(ver) (((ver >> 16) & 0xff0) | ((ver >> 8) & 0xf))
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#define x86cpuid_ver_GetModel(ver) (((ver >> 12) & 0xf0) | ((ver >> 4) & 0xf))
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#define x86cpuid_ver_GetStepping(ver) (ver & 0xf)
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int x86cpuid_GetFirm(const Cx86cpuid *p)
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{
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unsigned i;
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for (i = 0; i < sizeof(kVendors) / sizeof(kVendors[0]); i++)
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{
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const UInt32 *v = kVendors[i];
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if (v[0] == p->vendor[0]
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// && v[1] == p->vendor[1]
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// && v[2] == p->vendor[2]
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)
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return (int)i;
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}
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return -1;
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}
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BoolInt CPU_Is_InOrder()
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{
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Cx86cpuid p;
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UInt32 family, model;
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if (!x86cpuid_CheckAndRead(&p))
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return True;
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family = x86cpuid_ver_GetFamily(p.ver);
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model = x86cpuid_ver_GetModel(p.ver);
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switch (x86cpuid_GetFirm(&p))
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{
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case CPU_FIRM_INTEL: return (family < 6 || (family == 6 && (
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// In-Order Atom CPU
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model == 0x1C // 45 nm, N4xx, D4xx, N5xx, D5xx, 230, 330
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|| model == 0x26 // 45 nm, Z6xx
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|| model == 0x27 // 32 nm, Z2460
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|| model == 0x35 // 32 nm, Z2760
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|| model == 0x36 // 32 nm, N2xxx, D2xxx
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)));
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case CPU_FIRM_AMD: return (family < 5 || (family == 5 && (model < 6 || model == 0xA)));
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case CPU_FIRM_VIA: return (family < 6 || (family == 6 && model < 0xF));
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}
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return False; // v23 : unknown processors are not In-Order
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}
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*/
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#ifdef _WIN32
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#include "7zWindows.h"
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#endif
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#if !defined(MY_CPU_AMD64) && defined(_WIN32)
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/* for legacy SSE ia32: there is no user-space cpu instruction to check
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that OS supports SSE register storing/restoring on context switches.
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So we need some OS-specific function to check that it's safe to use SSE registers.
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*/
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Z7_FORCE_INLINE
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static BoolInt CPU_Sys_Is_SSE_Supported(void)
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{
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#ifdef _MSC_VER
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#pragma warning(push)
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#pragma warning(disable : 4996) // `GetVersion': was declared deprecated
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#endif
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/* low byte is major version of Windows
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We suppose that any Windows version since
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Windows2000 (major == 5) supports SSE registers */
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return (Byte)GetVersion() >= 5;
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#if defined(_MSC_VER)
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#pragma warning(pop)
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#endif
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}
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#define CHECK_SYS_SSE_SUPPORT if (!CPU_Sys_Is_SSE_Supported()) return False;
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#else
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#define CHECK_SYS_SSE_SUPPORT
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#endif
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#if !defined(MY_CPU_AMD64)
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BoolInt CPU_IsSupported_CMOV(void)
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{
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UInt32 a[4];
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if (!x86cpuid_Func_1(&a[0]))
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return 0;
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return (a[3] >> 15) & 1;
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}
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BoolInt CPU_IsSupported_SSE(void)
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{
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UInt32 a[4];
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CHECK_SYS_SSE_SUPPORT
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if (!x86cpuid_Func_1(&a[0]))
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return 0;
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return (a[3] >> 25) & 1;
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}
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BoolInt CPU_IsSupported_SSE2(void)
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{
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UInt32 a[4];
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CHECK_SYS_SSE_SUPPORT
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if (!x86cpuid_Func_1(&a[0]))
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return 0;
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return (a[3] >> 26) & 1;
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}
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#endif
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static UInt32 x86cpuid_Func_1_ECX(void)
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{
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UInt32 a[4];
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CHECK_SYS_SSE_SUPPORT
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if (!x86cpuid_Func_1(&a[0]))
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return 0;
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return a[2];
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}
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BoolInt CPU_IsSupported_AES(void)
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{
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return (x86cpuid_Func_1_ECX() >> 25) & 1;
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}
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BoolInt CPU_IsSupported_SSSE3(void)
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{
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return (x86cpuid_Func_1_ECX() >> 9) & 1;
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}
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BoolInt CPU_IsSupported_SSE41(void)
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{
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return (x86cpuid_Func_1_ECX() >> 19) & 1;
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}
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BoolInt CPU_IsSupported_SHA(void)
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{
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CHECK_SYS_SSE_SUPPORT
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if (z7_x86_cpuid_GetMaxFunc() < 7)
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return False;
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{
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UInt32 d[4];
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z7_x86_cpuid(d, 7);
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return (d[1] >> 29) & 1;
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}
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}
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/*
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MSVC: _xgetbv() intrinsic is available since VS2010SP1.
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MSVC also defines (_XCR_XFEATURE_ENABLED_MASK) macro in
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<immintrin.h> that we can use or check.
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For any 32-bit x86 we can use asm code in MSVC,
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but MSVC asm code is huge after compilation.
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So _xgetbv() is better
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ICC: _xgetbv() intrinsic is available (in what version of ICC?)
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ICC defines (__GNUC___) and it supports gnu assembler
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also ICC supports MASM style code with -use-msasm switch.
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but ICC doesn't support __attribute__((__target__))
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GCC/CLANG 9:
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_xgetbv() is macro that works via __builtin_ia32_xgetbv()
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and we need __attribute__((__target__("xsave")).
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But with __target__("xsave") the function will be not
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inlined to function that has no __target__("xsave") attribute.
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If we want _xgetbv() call inlining, then we should use asm version
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instead of calling _xgetbv().
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Note:intrinsic is broke before GCC 8.2:
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85684
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*/
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#if defined(__INTEL_COMPILER) && (__INTEL_COMPILER >= 1100) \
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|| defined(_MSC_VER) && (_MSC_VER >= 1600) && (_MSC_FULL_VER >= 160040219) \
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|| defined(__GNUC__) && (__GNUC__ >= 9) \
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|| defined(__clang__) && (__clang_major__ >= 9)
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// we define ATTRIB_XGETBV, if we want to use predefined _xgetbv() from compiler
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#if defined(__INTEL_COMPILER)
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#define ATTRIB_XGETBV
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#elif defined(__GNUC__) || defined(__clang__)
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// we don't define ATTRIB_XGETBV here, because asm version is better for inlining.
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// #define ATTRIB_XGETBV __attribute__((__target__("xsave")))
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#else
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#define ATTRIB_XGETBV
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#endif
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#endif
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#if defined(ATTRIB_XGETBV)
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#include <immintrin.h>
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#endif
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// XFEATURE_ENABLED_MASK/XCR0
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#define MY_XCR_XFEATURE_ENABLED_MASK 0
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#if defined(ATTRIB_XGETBV)
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ATTRIB_XGETBV
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#endif
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static UInt64 x86_xgetbv_0(UInt32 num)
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{
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#if defined(ATTRIB_XGETBV)
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{
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return
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#if (defined(_MSC_VER))
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_xgetbv(num);
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#else
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__builtin_ia32_xgetbv(
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#if !defined(__clang__)
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(int)
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#endif
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num);
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#endif
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}
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#elif defined(__GNUC__) || defined(__clang__) || defined(__SUNPRO_CC)
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UInt32 a, d;
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#if defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4))
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__asm__
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(
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"xgetbv"
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: "=a"(a), "=d"(d) : "c"(num) : "cc"
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);
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#else // is old gcc
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__asm__
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(
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".byte 0x0f, 0x01, 0xd0" "\n\t"
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: "=a"(a), "=d"(d) : "c"(num) : "cc"
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);
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#endif
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return ((UInt64)d << 32) | a;
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// return a;
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#elif defined(_MSC_VER) && !defined(MY_CPU_AMD64)
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UInt32 a, d;
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__asm {
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push eax
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push edx
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push ecx
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mov ecx, num;
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// xor ecx, ecx // = MY_XCR_XFEATURE_ENABLED_MASK
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_emit 0x0f
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_emit 0x01
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_emit 0xd0
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mov a, eax
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mov d, edx
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pop ecx
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pop edx
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pop eax
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}
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return ((UInt64)d << 32) | a;
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// return a;
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#else // it's unknown compiler
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// #error "Need xgetbv function"
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UNUSED_VAR(num)
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// for MSVC-X64 we could call external function from external file.
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/* Actually we had checked OSXSAVE/AVX in cpuid before.
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So it's expected that OS supports at least AVX and below. */
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// if (num != MY_XCR_XFEATURE_ENABLED_MASK) return 0; // if not XCR0
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return
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// (1 << 0) | // x87
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(1 << 1) // SSE
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| (1 << 2); // AVX
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#endif
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}
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#ifdef _WIN32
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/*
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Windows versions do not know about new ISA extensions that
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can be introduced. But we still can use new extensions,
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even if Windows doesn't report about supporting them,
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But we can use new extensions, only if Windows knows about new ISA extension
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that changes the number or size of registers: SSE, AVX/XSAVE, AVX512
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So it's enough to check
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MY_PF_AVX_INSTRUCTIONS_AVAILABLE
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instead of
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MY_PF_AVX2_INSTRUCTIONS_AVAILABLE
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*/
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#define MY_PF_XSAVE_ENABLED 17
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// #define MY_PF_SSSE3_INSTRUCTIONS_AVAILABLE 36
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// #define MY_PF_SSE4_1_INSTRUCTIONS_AVAILABLE 37
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// #define MY_PF_SSE4_2_INSTRUCTIONS_AVAILABLE 38
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// #define MY_PF_AVX_INSTRUCTIONS_AVAILABLE 39
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// #define MY_PF_AVX2_INSTRUCTIONS_AVAILABLE 40
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// #define MY_PF_AVX512F_INSTRUCTIONS_AVAILABLE 41
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#endif
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BoolInt CPU_IsSupported_AVX(void)
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{
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#ifdef _WIN32
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if (!IsProcessorFeaturePresent(MY_PF_XSAVE_ENABLED))
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return False;
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/* PF_AVX_INSTRUCTIONS_AVAILABLE probably is supported starting from
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some latest Win10 revisions. But we need AVX in older Windows also.
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So we don't use the following check: */
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/*
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if (!IsProcessorFeaturePresent(MY_PF_AVX_INSTRUCTIONS_AVAILABLE))
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return False;
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*/
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#endif
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/*
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OS must use new special XSAVE/XRSTOR instructions to save
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AVX registers when it required for context switching.
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At OS statring:
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OS sets CR4.OSXSAVE flag to signal the processor that OS supports the XSAVE extensions.
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Also OS sets bitmask in XCR0 register that defines what
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registers will be processed by XSAVE instruction:
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XCR0.SSE[bit 0] - x87 registers and state
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XCR0.SSE[bit 1] - SSE registers and state
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XCR0.AVX[bit 2] - AVX registers and state
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CR4.OSXSAVE is reflected to CPUID.1:ECX.OSXSAVE[bit 27].
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So we can read that bit in user-space.
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XCR0 is available for reading in user-space by new XGETBV instruction.
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*/
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{
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const UInt32 c = x86cpuid_Func_1_ECX();
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if (0 == (1
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& (c >> 28) // AVX instructions are supported by hardware
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& (c >> 27))) // OSXSAVE bit: XSAVE and related instructions are enabled by OS.
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return False;
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}
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/* also we can check
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CPUID.1:ECX.XSAVE [bit 26] : that shows that
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XSAVE, XRESTOR, XSETBV, XGETBV instructions are supported by hardware.
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But that check is redundant, because if OSXSAVE bit is set, then XSAVE is also set */
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/* If OS have enabled XSAVE extension instructions (OSXSAVE == 1),
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in most cases we expect that OS also will support storing/restoring
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for AVX and SSE states at least.
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But to be ensure for that we call user-space instruction
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XGETBV(0) to get XCR0 value that contains bitmask that defines
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what exact states(registers) OS have enabled for storing/restoring.
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*/
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{
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const UInt32 bm = (UInt32)x86_xgetbv_0(MY_XCR_XFEATURE_ENABLED_MASK);
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// printf("\n=== XGetBV=%d\n", bm);
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return 1
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& (bm >> 1) // SSE state is supported (set by OS) for storing/restoring
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& (bm >> 2); // AVX state is supported (set by OS) for storing/restoring
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}
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// since Win7SP1: we can use GetEnabledXStateFeatures();
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}
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BoolInt CPU_IsSupported_AVX2(void)
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{
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if (!CPU_IsSupported_AVX())
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return False;
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if (z7_x86_cpuid_GetMaxFunc() < 7)
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return False;
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{
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UInt32 d[4];
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z7_x86_cpuid(d, 7);
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// printf("\ncpuid(7): ebx=%8x ecx=%8x\n", d[1], d[2]);
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return 1
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& (d[1] >> 5); // avx2
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}
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}
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BoolInt CPU_IsSupported_VAES_AVX2(void)
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{
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if (!CPU_IsSupported_AVX())
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return False;
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if (z7_x86_cpuid_GetMaxFunc() < 7)
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return False;
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{
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UInt32 d[4];
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z7_x86_cpuid(d, 7);
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// printf("\ncpuid(7): ebx=%8x ecx=%8x\n", d[1], d[2]);
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return 1
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& (d[1] >> 5) // avx2
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// & (d[1] >> 31) // avx512vl
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& (d[2] >> 9); // vaes // VEX-256/EVEX
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}
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}
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BoolInt CPU_IsSupported_PageGB(void)
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{
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CHECK_CPUID_IS_SUPPORTED
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{
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UInt32 d[4];
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z7_x86_cpuid(d, 0x80000000);
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if (d[0] < 0x80000001)
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return False;
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z7_x86_cpuid(d, 0x80000001);
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return (d[3] >> 26) & 1;
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}
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}
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#elif defined(MY_CPU_ARM_OR_ARM64)
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#ifdef _WIN32
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#include "7zWindows.h"
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BoolInt CPU_IsSupported_CRC32(void) { return IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) ? 1 : 0; }
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BoolInt CPU_IsSupported_CRYPTO(void) { return IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) ? 1 : 0; }
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BoolInt CPU_IsSupported_NEON(void) { return IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE) ? 1 : 0; }
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#else
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#if defined(__APPLE__)
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/*
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#include <stdio.h>
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#include <string.h>
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static void Print_sysctlbyname(const char *name)
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{
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size_t bufSize = 256;
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char buf[256];
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int res = sysctlbyname(name, &buf, &bufSize, NULL, 0);
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{
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int i;
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printf("\nres = %d : %s : '%s' : bufSize = %d, numeric", res, name, buf, (unsigned)bufSize);
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for (i = 0; i < 20; i++)
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printf(" %2x", (unsigned)(Byte)buf[i]);
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}
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}
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*/
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/*
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Print_sysctlbyname("hw.pagesize");
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Print_sysctlbyname("machdep.cpu.brand_string");
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*/
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static BoolInt z7_sysctlbyname_Get_BoolInt(const char *name)
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{
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UInt32 val = 0;
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if (z7_sysctlbyname_Get_UInt32(name, &val) == 0 && val == 1)
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return 1;
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return 0;
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}
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BoolInt CPU_IsSupported_CRC32(void)
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{
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return z7_sysctlbyname_Get_BoolInt("hw.optional.armv8_crc32");
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}
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BoolInt CPU_IsSupported_NEON(void)
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{
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return z7_sysctlbyname_Get_BoolInt("hw.optional.neon");
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}
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#ifdef MY_CPU_ARM64
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#define APPLE_CRYPTO_SUPPORT_VAL 1
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#else
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#define APPLE_CRYPTO_SUPPORT_VAL 0
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#endif
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BoolInt CPU_IsSupported_SHA1(void) { return APPLE_CRYPTO_SUPPORT_VAL; }
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BoolInt CPU_IsSupported_SHA2(void) { return APPLE_CRYPTO_SUPPORT_VAL; }
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BoolInt CPU_IsSupported_AES (void) { return APPLE_CRYPTO_SUPPORT_VAL; }
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#else // __APPLE__
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#include <sys/auxv.h>
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|
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#define USE_HWCAP
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|
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#ifdef USE_HWCAP
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|
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#include <asm/hwcap.h>
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|
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#define MY_HWCAP_CHECK_FUNC_2(name1, name2) \
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BoolInt CPU_IsSupported_ ## name1() { return (getauxval(AT_HWCAP) & (HWCAP_ ## name2)) ? 1 : 0; }
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|
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#ifdef MY_CPU_ARM64
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#define MY_HWCAP_CHECK_FUNC(name) \
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MY_HWCAP_CHECK_FUNC_2(name, name)
|
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MY_HWCAP_CHECK_FUNC_2(NEON, ASIMD)
|
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// MY_HWCAP_CHECK_FUNC (ASIMD)
|
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#elif defined(MY_CPU_ARM)
|
|
#define MY_HWCAP_CHECK_FUNC(name) \
|
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BoolInt CPU_IsSupported_ ## name() { return (getauxval(AT_HWCAP2) & (HWCAP2_ ## name)) ? 1 : 0; }
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|
MY_HWCAP_CHECK_FUNC_2(NEON, NEON)
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#endif
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|
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#else // USE_HWCAP
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|
|
#define MY_HWCAP_CHECK_FUNC(name) \
|
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BoolInt CPU_IsSupported_ ## name() { return 0; }
|
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MY_HWCAP_CHECK_FUNC(NEON)
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|
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#endif // USE_HWCAP
|
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|
|
MY_HWCAP_CHECK_FUNC (CRC32)
|
|
MY_HWCAP_CHECK_FUNC (SHA1)
|
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MY_HWCAP_CHECK_FUNC (SHA2)
|
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MY_HWCAP_CHECK_FUNC (AES)
|
|
|
|
#endif // __APPLE__
|
|
#endif // _WIN32
|
|
|
|
#endif // MY_CPU_ARM_OR_ARM64
|
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|
|
|
|
|
|
#ifdef __APPLE__
|
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|
|
#include <sys/sysctl.h>
|
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|
|
int z7_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize)
|
|
{
|
|
return sysctlbyname(name, buf, bufSize, NULL, 0);
|
|
}
|
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|
|
int z7_sysctlbyname_Get_UInt32(const char *name, UInt32 *val)
|
|
{
|
|
size_t bufSize = sizeof(*val);
|
|
const int res = z7_sysctlbyname_Get(name, val, &bufSize);
|
|
if (res == 0 && bufSize != sizeof(*val))
|
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return EFAULT;
|
|
return res;
|
|
}
|
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|
|
#endif
|