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420 lines
11 KiB
C
420 lines
11 KiB
C
/* Bra.c -- Branch converters for RISC code
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2023-04-02 : Igor Pavlov : Public domain */
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#include "Precomp.h"
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#include "Bra.h"
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#include "CpuArch.h"
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#include "RotateDefs.h"
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#if defined(MY_CPU_SIZEOF_POINTER) \
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&& ( MY_CPU_SIZEOF_POINTER == 4 \
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|| MY_CPU_SIZEOF_POINTER == 8)
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#define BR_CONV_USE_OPT_PC_PTR
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#endif
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#ifdef BR_CONV_USE_OPT_PC_PTR
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#define BR_PC_INIT pc -= (UInt32)(SizeT)p;
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#define BR_PC_GET (pc + (UInt32)(SizeT)p)
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#else
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#define BR_PC_INIT pc += (UInt32)size;
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#define BR_PC_GET (pc - (UInt32)(SizeT)(lim - p))
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// #define BR_PC_INIT
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// #define BR_PC_GET (pc + (UInt32)(SizeT)(p - data))
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#endif
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#define BR_CONVERT_VAL(v, c) if (encoding) v += c; else v -= c;
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// #define BR_CONVERT_VAL(v, c) if (!encoding) c = (UInt32)0 - c; v += c;
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#define Z7_BRANCH_CONV(name) z7_BranchConv_ ## name
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#define Z7_BRANCH_FUNC_MAIN(name) \
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static \
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Z7_FORCE_INLINE \
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Z7_ATTRIB_NO_VECTOR \
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Byte *Z7_BRANCH_CONV(name)(Byte *p, SizeT size, UInt32 pc, int encoding)
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#define Z7_BRANCH_FUNC_IMP(name, m, encoding) \
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Z7_NO_INLINE \
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Z7_ATTRIB_NO_VECTOR \
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Byte *m(name)(Byte *data, SizeT size, UInt32 pc) \
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{ return Z7_BRANCH_CONV(name)(data, size, pc, encoding); } \
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#ifdef Z7_EXTRACT_ONLY
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#define Z7_BRANCH_FUNCS_IMP(name) \
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Z7_BRANCH_FUNC_IMP(name, Z7_BRANCH_CONV_DEC, 0)
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#else
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#define Z7_BRANCH_FUNCS_IMP(name) \
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Z7_BRANCH_FUNC_IMP(name, Z7_BRANCH_CONV_DEC, 0) \
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Z7_BRANCH_FUNC_IMP(name, Z7_BRANCH_CONV_ENC, 1)
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#endif
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#if defined(__clang__)
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#define BR_EXTERNAL_FOR
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#define BR_NEXT_ITERATION continue;
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#else
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#define BR_EXTERNAL_FOR for (;;)
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#define BR_NEXT_ITERATION break;
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#endif
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#if defined(__clang__) && (__clang_major__ >= 8) \
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|| defined(__GNUC__) && (__GNUC__ >= 1000) \
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// GCC is not good for __builtin_expect() here
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/* || defined(_MSC_VER) && (_MSC_VER >= 1920) */
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// #define Z7_unlikely [[unlikely]]
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// #define Z7_LIKELY(x) (__builtin_expect((x), 1))
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#define Z7_UNLIKELY(x) (__builtin_expect((x), 0))
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// #define Z7_likely [[likely]]
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#else
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// #define Z7_LIKELY(x) (x)
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#define Z7_UNLIKELY(x) (x)
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// #define Z7_likely
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#endif
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Z7_BRANCH_FUNC_MAIN(ARM64)
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{
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// Byte *p = data;
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const Byte *lim;
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const UInt32 flag = (UInt32)1 << (24 - 4);
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const UInt32 mask = ((UInt32)1 << 24) - (flag << 1);
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size &= ~(SizeT)3;
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// if (size == 0) return p;
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lim = p + size;
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BR_PC_INIT
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pc -= 4; // because (p) will point to next instruction
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BR_EXTERNAL_FOR
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{
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// Z7_PRAGMA_OPT_DISABLE_LOOP_UNROLL_VECTORIZE
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for (;;)
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{
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UInt32 v;
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if Z7_UNLIKELY(p == lim)
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return p;
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v = GetUi32a(p);
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p += 4;
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if Z7_UNLIKELY(((v - 0x94000000) & 0xfc000000) == 0)
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{
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UInt32 c = BR_PC_GET >> 2;
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BR_CONVERT_VAL(v, c)
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v &= 0x03ffffff;
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v |= 0x94000000;
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SetUi32a(p - 4, v)
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BR_NEXT_ITERATION
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}
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// v = rotlFixed(v, 8); v += (flag << 8) - 0x90; if Z7_UNLIKELY((v & ((mask << 8) + 0x9f)) == 0)
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v -= 0x90000000; if Z7_UNLIKELY((v & 0x9f000000) == 0)
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{
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UInt32 z, c;
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// v = rotrFixed(v, 8);
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v += flag; if Z7_UNLIKELY(v & mask) continue;
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z = (v & 0xffffffe0) | (v >> 26);
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c = (BR_PC_GET >> (12 - 3)) & ~(UInt32)7;
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BR_CONVERT_VAL(z, c)
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v &= 0x1f;
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v |= 0x90000000;
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v |= z << 26;
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v |= 0x00ffffe0 & ((z & (((flag << 1) - 1))) - flag);
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SetUi32a(p - 4, v)
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}
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}
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}
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}
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Z7_BRANCH_FUNCS_IMP(ARM64)
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Z7_BRANCH_FUNC_MAIN(ARM)
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{
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// Byte *p = data;
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const Byte *lim;
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size &= ~(SizeT)3;
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lim = p + size;
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BR_PC_INIT
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/* in ARM: branch offset is relative to the +2 instructions from current instruction.
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(p) will point to next instruction */
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pc += 8 - 4;
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for (;;)
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{
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for (;;)
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{
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if Z7_UNLIKELY(p >= lim) { return p; } p += 4; if Z7_UNLIKELY(p[-1] == 0xeb) break;
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if Z7_UNLIKELY(p >= lim) { return p; } p += 4; if Z7_UNLIKELY(p[-1] == 0xeb) break;
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}
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{
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UInt32 v = GetUi32a(p - 4);
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UInt32 c = BR_PC_GET >> 2;
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BR_CONVERT_VAL(v, c)
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v &= 0x00ffffff;
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v |= 0xeb000000;
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SetUi32a(p - 4, v)
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}
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}
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}
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Z7_BRANCH_FUNCS_IMP(ARM)
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Z7_BRANCH_FUNC_MAIN(PPC)
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{
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// Byte *p = data;
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const Byte *lim;
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size &= ~(SizeT)3;
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lim = p + size;
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BR_PC_INIT
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pc -= 4; // because (p) will point to next instruction
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for (;;)
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{
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UInt32 v;
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for (;;)
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{
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if Z7_UNLIKELY(p == lim)
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return p;
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// v = GetBe32a(p);
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v = *(UInt32 *)(void *)p;
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p += 4;
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// if ((v & 0xfc000003) == 0x48000001) break;
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// if ((p[-4] & 0xFC) == 0x48 && (p[-1] & 3) == 1) break;
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if Z7_UNLIKELY(
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((v - Z7_CONV_BE_TO_NATIVE_CONST32(0x48000001))
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& Z7_CONV_BE_TO_NATIVE_CONST32(0xfc000003)) == 0) break;
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}
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{
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v = Z7_CONV_NATIVE_TO_BE_32(v);
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{
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UInt32 c = BR_PC_GET;
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BR_CONVERT_VAL(v, c)
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}
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v &= 0x03ffffff;
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v |= 0x48000000;
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SetBe32a(p - 4, v)
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}
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}
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}
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Z7_BRANCH_FUNCS_IMP(PPC)
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#ifdef Z7_CPU_FAST_ROTATE_SUPPORTED
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#define BR_SPARC_USE_ROTATE
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#endif
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Z7_BRANCH_FUNC_MAIN(SPARC)
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{
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// Byte *p = data;
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const Byte *lim;
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const UInt32 flag = (UInt32)1 << 22;
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size &= ~(SizeT)3;
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lim = p + size;
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BR_PC_INIT
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pc -= 4; // because (p) will point to next instruction
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for (;;)
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{
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UInt32 v;
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for (;;)
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{
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if Z7_UNLIKELY(p == lim)
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return p;
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/* // the code without GetBe32a():
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{ const UInt32 v = GetUi16a(p) & 0xc0ff; p += 4; if (v == 0x40 || v == 0xc07f) break; }
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*/
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v = GetBe32a(p);
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p += 4;
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#ifdef BR_SPARC_USE_ROTATE
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v = rotlFixed(v, 2);
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v += (flag << 2) - 1;
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if Z7_UNLIKELY((v & (3 - (flag << 3))) == 0)
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#else
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v += (UInt32)5 << 29;
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v ^= (UInt32)7 << 29;
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v += flag;
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if Z7_UNLIKELY((v & (0 - (flag << 1))) == 0)
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#endif
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break;
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}
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{
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// UInt32 v = GetBe32a(p - 4);
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#ifndef BR_SPARC_USE_ROTATE
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v <<= 2;
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#endif
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{
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UInt32 c = BR_PC_GET;
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BR_CONVERT_VAL(v, c)
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}
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v &= (flag << 3) - 1;
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#ifdef BR_SPARC_USE_ROTATE
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v -= (flag << 2) - 1;
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v = rotrFixed(v, 2);
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#else
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v -= (flag << 2);
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v >>= 2;
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v |= (UInt32)1 << 30;
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#endif
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SetBe32a(p - 4, v)
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}
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}
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}
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Z7_BRANCH_FUNCS_IMP(SPARC)
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Z7_BRANCH_FUNC_MAIN(ARMT)
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{
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// Byte *p = data;
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Byte *lim;
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size &= ~(SizeT)1;
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// if (size == 0) return p;
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if (size <= 2) return p;
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size -= 2;
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lim = p + size;
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BR_PC_INIT
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/* in ARM: branch offset is relative to the +2 instructions from current instruction.
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(p) will point to the +2 instructions from current instruction */
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// pc += 4 - 4;
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// if (encoding) pc -= 0xf800 << 1; else pc += 0xf800 << 1;
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// #define ARMT_TAIL_PROC { goto armt_tail; }
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#define ARMT_TAIL_PROC { return p; }
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do
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{
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/* in MSVC 32-bit x86 compilers:
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UInt32 version : it loads value from memory with movzx
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Byte version : it loads value to 8-bit register (AL/CL)
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movzx version is slightly faster in some cpus
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*/
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unsigned b1;
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// Byte / unsigned
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b1 = p[1];
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// optimized version to reduce one (p >= lim) check:
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// unsigned a1 = p[1]; b1 = p[3]; p += 2; if Z7_LIKELY((b1 & (a1 ^ 8)) < 0xf8)
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for (;;)
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{
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unsigned b3; // Byte / UInt32
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/* (Byte)(b3) normalization can use low byte computations in MSVC.
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It gives smaller code, and no loss of speed in some compilers/cpus.
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But new MSVC 32-bit x86 compilers use more slow load
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from memory to low byte register in that case.
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So we try to use full 32-bit computations for faster code.
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*/
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// if (p >= lim) { ARMT_TAIL_PROC } b3 = b1 + 8; b1 = p[3]; p += 2; if ((b3 & b1) >= 0xf8) break;
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if Z7_UNLIKELY(p >= lim) { ARMT_TAIL_PROC } b3 = p[3]; p += 2; if Z7_UNLIKELY((b3 & (b1 ^ 8)) >= 0xf8) break;
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if Z7_UNLIKELY(p >= lim) { ARMT_TAIL_PROC } b1 = p[3]; p += 2; if Z7_UNLIKELY((b1 & (b3 ^ 8)) >= 0xf8) break;
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}
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{
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/* we can adjust pc for (0xf800) to rid of (& 0x7FF) operation.
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But gcc/clang for arm64 can use bfi instruction for full code here */
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UInt32 v =
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((UInt32)GetUi16a(p - 2) << 11) |
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((UInt32)GetUi16a(p) & 0x7FF);
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/*
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UInt32 v =
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((UInt32)p[1 - 2] << 19)
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+ (((UInt32)p[1] & 0x7) << 8)
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+ (((UInt32)p[-2] << 11))
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+ (p[0]);
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*/
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p += 2;
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{
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UInt32 c = BR_PC_GET >> 1;
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BR_CONVERT_VAL(v, c)
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}
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SetUi16a(p - 4, (UInt16)(((v >> 11) & 0x7ff) | 0xf000))
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SetUi16a(p - 2, (UInt16)(v | 0xf800))
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/*
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p[-4] = (Byte)(v >> 11);
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p[-3] = (Byte)(0xf0 | ((v >> 19) & 0x7));
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p[-2] = (Byte)v;
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p[-1] = (Byte)(0xf8 | (v >> 8));
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*/
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}
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}
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while (p < lim);
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return p;
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// armt_tail:
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// if ((Byte)((lim[1] & 0xf8)) != 0xf0) { lim += 2; } return lim;
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// return (Byte *)(lim + ((Byte)((lim[1] ^ 0xf0) & 0xf8) == 0 ? 0 : 2));
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// return (Byte *)(lim + (((lim[1] ^ ~0xfu) & ~7u) == 0 ? 0 : 2));
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// return (Byte *)(lim + 2 - (((((unsigned)lim[1] ^ 8) + 8) >> 7) & 2));
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}
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Z7_BRANCH_FUNCS_IMP(ARMT)
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// #define BR_IA64_NO_INLINE
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Z7_BRANCH_FUNC_MAIN(IA64)
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{
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// Byte *p = data;
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const Byte *lim;
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size &= ~(SizeT)15;
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lim = p + size;
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pc -= 1 << 4;
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pc >>= 4 - 1;
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// pc -= 1 << 1;
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for (;;)
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{
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unsigned m;
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for (;;)
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{
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if Z7_UNLIKELY(p == lim)
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return p;
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m = (unsigned)((UInt32)0x334b0000 >> (*p & 0x1e));
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p += 16;
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pc += 1 << 1;
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if (m &= 3)
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break;
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}
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{
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p += (ptrdiff_t)m * 5 - 20; // negative value is expected here.
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do
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{
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const UInt32 t =
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#if defined(MY_CPU_X86_OR_AMD64)
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// we use 32-bit load here to reduce code size on x86:
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GetUi32(p);
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#else
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GetUi16(p);
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#endif
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UInt32 z = GetUi32(p + 1) >> m;
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p += 5;
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if (((t >> m) & (0x70 << 1)) == 0
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&& ((z - (0x5000000 << 1)) & (0xf000000 << 1)) == 0)
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{
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UInt32 v = (UInt32)((0x8fffff << 1) | 1) & z;
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z ^= v;
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#ifdef BR_IA64_NO_INLINE
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v |= (v & ((UInt32)1 << (23 + 1))) >> 3;
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{
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UInt32 c = pc;
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BR_CONVERT_VAL(v, c)
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}
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v &= (0x1fffff << 1) | 1;
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#else
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{
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if (encoding)
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{
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// pc &= ~(0xc00000 << 1); // we just need to clear at least 2 bits
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pc &= (0x1fffff << 1) | 1;
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v += pc;
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}
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else
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{
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// pc |= 0xc00000 << 1; // we need to set at least 2 bits
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pc |= ~(UInt32)((0x1fffff << 1) | 1);
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v -= pc;
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}
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}
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v &= ~(UInt32)(0x600000 << 1);
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#endif
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v += (0x700000 << 1);
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v &= (0x8fffff << 1) | 1;
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z |= v;
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z <<= m;
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SetUi32(p + 1 - 5, z)
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}
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m++;
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}
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while (m &= 3); // while (m < 4);
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}
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}
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}
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Z7_BRANCH_FUNCS_IMP(IA64)
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