mirror of https://github.com/ZDoom/gzdoom.git
- implemented unwind info for Linux and macOS - now to fix the bugs that cannot be fixed when the documentation is as useless as it is for those platforms..
This commit is contained in:
Magnus Norddahl
parent
19df662348
commit
37e33c6609
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@ -291,36 +291,33 @@ extern "C"
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static void WriteLength(TArray<uint8_t> &stream, unsigned int pos, unsigned int v)
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{
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stream[pos] = v >> 24;
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stream[pos + 1] = (v >> 16) & 0xff;
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stream[pos + 2] = (v >> 8) & 0xff;
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stream[pos + 3] = v & 0xff;
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*(uint64_t*)(&stream[pos]) = v;
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}
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static void WriteUInt64(TArray<uint8_t> &stream, uint64_t v)
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{
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stream.Push(v >> 56);
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stream.Push((v >> 48) & 0xff);
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stream.Push((v >> 40) & 0xff);
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stream.Push((v >> 32) & 0xff);
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stream.Push((v >> 24) & 0xff);
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stream.Push((v >> 16) & 0xff);
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stream.Push((v >> 8) & 0xff);
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stream.Push(v & 0xff);
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stream.Push((v >> 8) & 0xff);
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stream.Push((v >> 16) & 0xff);
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stream.Push((v >> 24) & 0xff);
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stream.Push((v >> 32) & 0xff);
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stream.Push((v >> 40) & 0xff);
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stream.Push((v >> 48) & 0xff);
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stream.Push(v >> 56);
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}
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static void WriteUInt32(TArray<uint8_t> &stream, uint32_t v)
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{
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stream.Push(v >> 24);
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stream.Push((v >> 16) & 0xff);
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stream.Push((v >> 8) & 0xff);
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stream.Push(v & 0xff);
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stream.Push((v >> 8) & 0xff);
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stream.Push((v >> 16) & 0xff);
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stream.Push(v >> 24);
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}
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static void WriteUInt16(TArray<uint8_t> &stream, uint16_t v)
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{
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stream.Push((v >> 8) & 0xff);
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stream.Push(v & 0xff);
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stream.Push((v >> 8) & 0xff);
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}
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static void WriteUInt8(TArray<uint8_t> &stream, uint8_t v)
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@ -357,21 +354,11 @@ static void WriteSLEB128(TArray<uint8_t> &stream, int32_t v)
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}
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}
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struct FrameDesc
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{
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int minInstAlignment = 4;
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int dataAlignmentFactor = -4;
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uint8_t returnAddressReg = 0;
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uint32_t cieLocation = 0;
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uint64_t functionStart = 0;
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uint64_t functionSize = 0;
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};
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static void WriteCIE(TArray<uint8_t> &stream, const TArray<uint8_t> &cieInstructions, uint8_t returnAddressReg, int minInstAlignment, int dataAlignmentFactor)
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{
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WriteUInt32(stream, 0xffffffff); // this is a 64-bit entry
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unsigned int lengthPos = stream.Size();
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WriteUInt32(stream, 0); // Length
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WriteUInt64(stream, 0); // Length
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WriteUInt32(stream, 0); // CIE ID
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WriteUInt8(stream, 1); // CIE Version
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@ -387,7 +374,7 @@ static void WriteCIE(TArray<uint8_t> &stream, const TArray<uint8_t> &cieInstruct
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stream.Push(cieInstructions[i]);
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// Padding and update length field
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unsigned int length = stream.Size() - lengthPos;
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unsigned int length = stream.Size() - lengthPos - 8;
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int padding = stream.Size() % 4;
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for (int i = 0; i <= padding; i++) WriteUInt8(stream, 0);
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WriteLength(stream, lengthPos, length);
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@ -397,8 +384,9 @@ static void WriteFDE(TArray<uint8_t> &stream, const TArray<uint8_t> &fdeInstruct
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{
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uint32_t offsetToCIE = stream.Size() - cieLocation;
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WriteUInt32(stream, 0xffffffff); // this is a 64-bit entry
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unsigned int lengthPos = stream.Size();
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WriteUInt32(stream, 0); // Length
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WriteUInt64(stream, 0); // Length
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WriteUInt32(stream, offsetToCIE);
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functionStart = stream.Size();
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@ -409,7 +397,7 @@ static void WriteFDE(TArray<uint8_t> &stream, const TArray<uint8_t> &fdeInstruct
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stream.Push(fdeInstructions[i]);
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// Padding and update length field
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unsigned int length = stream.Size() - lengthPos;
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unsigned int length = stream.Size() - lengthPos - 8;
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int padding = stream.Size() % 4;
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for (int i = 0; i <= padding; i++) WriteUInt8(stream, 0);
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WriteLength(stream, lengthPos, length);
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@ -452,19 +440,45 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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X86Emitter *emitter = assembler.asEmitter();
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// Build .eh_frame:
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// (see appendix D.6 "Call Frame Information Example" in the DWARF 5 spec)
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//
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// The documentation for this can be found in the DWARF standard
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// The x64 specific details are described in "System V Application Binary Interface AMD64 Architecture Processor Supplement"
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//
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// See appendix D.6 "Call Frame Information Example" in the DWARF 5 spec.
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// Asmjit -> DWARF register id
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int dwarfRegId[16];
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dwarfRegId[X86Gp::kIdAx] = 0;
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dwarfRegId[X86Gp::kIdDx] = 1;
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dwarfRegId[X86Gp::kIdCx] = 2;
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dwarfRegId[X86Gp::kIdBx] = 3;
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dwarfRegId[X86Gp::kIdSi] = 4;
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dwarfRegId[X86Gp::kIdDi] = 5;
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dwarfRegId[X86Gp::kIdBp] = 6;
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dwarfRegId[X86Gp::kIdSp] = 7;
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dwarfRegId[X86Gp::kIdR8] = 8;
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dwarfRegId[X86Gp::kIdR9] = 9;
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dwarfRegId[X86Gp::kIdR10] = 10;
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dwarfRegId[X86Gp::kIdR11] = 11;
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dwarfRegId[X86Gp::kIdR12] = 12;
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dwarfRegId[X86Gp::kIdR13] = 13;
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dwarfRegId[X86Gp::kIdR14] = 14;
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dwarfRegId[X86Gp::kIdR15] = 15;
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int dwarfRegRAId = 16;
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int dwarfRegXmmId = 17;
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TArray<uint8_t> cieInstructions;
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TArray<uint8_t> fdeInstructions;
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uint64_t lastOffset = 0;
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int minInstAlignment = 4; // To do: is this correct?
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int dataAlignmentFactor = -4; // To do: is this correct?
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uint8_t returnAddressReg = 0; // To do: get this from asmjit
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int minInstAlignment = 1;
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int dataAlignmentFactor = -4;
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uint8_t returnAddressReg = dwarfRegRAId;
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// To do: do we need to write register defaults into the CIE or does the defaults match the x64 calling convention?
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// Great! the "System V Application Binary Interface AMD64 Architecture Processor Supplement" doesn't say what the defaults are..
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// Note: this must match exactly what X86Internal::emitProlog does
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// Note: the following code must match exactly what X86Internal::emitProlog does
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X86Gp zsp = emitter->zsp(); // ESP|RSP register.
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X86Gp zbp = emitter->zsp(); // EBP|RBP register.
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@ -473,6 +487,8 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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X86Gp saReg = emitter->zsp(); // Stack-arguments base register.
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uint32_t gpSaved = layout.getSavedRegs(X86Reg::kKindGp);
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int saveoffset = 0;
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if (layout.hasPreservedFP())
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{
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// Emit: 'push zbp'
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@ -481,8 +497,9 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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emitter->push(zbp);
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WriteAdvanceLoc(fdeInstructions, assembler.getOffset(), lastOffset);
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// WriteXX(cieInstructions, UWOP_PUSH_NONVOL);
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// WriteXX(cieInstructions, X86Gp::kIdBp);
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WriteUInt8(fdeInstructions, (2 << 6) | dwarfRegId[X86Gp::kIdBp]); // DW_CFA_offset
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WriteULEB128(fdeInstructions, saveoffset);
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saveoffset += 2;
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emitter->mov(zbp, zsp);
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}
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@ -497,8 +514,9 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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emitter->push(gpReg);
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WriteAdvanceLoc(fdeInstructions, assembler.getOffset(), lastOffset);
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// WriteXX(cieInstructions, UWOP_PUSH_NONVOL);
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// WriteXX(cieInstructions, regId);
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WriteUInt8(fdeInstructions, (2 << 6) | dwarfRegId[regId]); // DW_CFA_offset
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WriteULEB128(fdeInstructions, saveoffset);
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saveoffset += 2;
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}
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}
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@ -528,6 +546,8 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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WriteAdvanceLoc(fdeInstructions, assembler.getOffset(), lastOffset);
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WriteUInt8(fdeInstructions, 0x0e); // DW_CFA_def_cfa_offset
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WriteULEB128(fdeInstructions, stackadjust);
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saveoffset += layout.getStackAdjustment() / dataAlignmentFactor;
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}
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if (layout.hasDynamicAlignment() && layout.hasDsaSlotUsed())
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@ -540,6 +560,7 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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uint32_t xmmSaved = layout.getSavedRegs(X86Reg::kKindVec);
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if (xmmSaved)
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{
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saveoffset += layout.getVecStackOffset() / dataAlignmentFactor;
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X86Mem vecBase = x86::ptr(zsp, layout.getVecStackOffset());
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X86Reg vecReg = x86::xmm(0);
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bool avx = layout.isAvxEnabled();
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@ -556,8 +577,9 @@ static TArray<uint8_t> CreateUnwindInfoUnix(asmjit::CCFunc *func, unsigned int &
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vecBase.addOffsetLo32(static_cast<int32_t>(vecSize));
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WriteAdvanceLoc(fdeInstructions, assembler.getOffset(), lastOffset);
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// WriteXX(cieInstructions, UWOP_SAVE_XMM128);
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// WriteXX(cieInstructions, regId);
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WriteUInt8(fdeInstructions, (2 << 6) | (dwarfRegXmmId + regId)); // DW_CFA_offset
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WriteULEB128(fdeInstructions, saveoffset);
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saveoffset += 2;
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}
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}
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