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dda5ddd3c2
registers AMD64 provides, this routine still needs to be written as self- modifying code for maximum performance. The additional registers do allow for further optimization over the x86 version by allowing all four pixels to be in flight at the same time. The end result is that AMD64 ASM is about 2.18 times faster than AMD64 C and about 1.06 times faster than x86 ASM. (For further comparison, AMD64 C and x86 C are practically the same for this function.) Should I port any more assembly to AMD64, mvlineasm4 is the most likely candidate, but it's not used enough at this point to bother. Also, this may or may not work with Linux at the moment, since it doesn't have the eh_handler metadata. Win64 is easier, since I just need to structure the function prologue and epilogue properly and use some assembler directives/macros to automatically generate the metadata. And that brings up another point: You need YASM to assemble the AMD64 code, because NASM doesn't support the Win64 metadata directives. - Added an SSE version of DoBlending. This is strictly C intrinsics. VC++ still throws around unneccessary register moves. GCC seems to be pretty close to optimal, requiring only about 2 cycles/color. They're both faster than my hand-written MMX routine, so I don't need to feel bad about not hand-optimizing this for x64 builds. - Removed an extra instruction from DoBlending_MMX, transposed two instructions, and unrolled it once, shaving off about 80 cycles from the time required to blend 256 palette entries. Why? Because I tried writing a C version of the routine using compiler intrinsics and was appalled by all the extra movq's VC++ added to the code. GCC was better, but still generated extra instructions. I only wanted a C version because I can't use inline assembly with VC++'s x64 compiler, and x64 assembly is a bit of a pain. (It's a pain because Linux and Windows have different calling conventions, and you need to maintain extra metadata for functions.) So, the assembly version stays and the C version stays out. - Removed all the pixel doubling r_detail modes, since the one platform they were intended to assist (486) actually sees very little benefit from them. - Rewrote CheckMMX in C and renamed it to CheckCPU. - Fixed: CPUID function 0x80000005 is specified to return detailed L1 cache only for AMD processors, so we must not use it on other architectures, or we end up overwriting the L1 cache line size with 0 or some other number we don't actually understand. SVN r1134 (trunk)
200 lines
5.5 KiB
NASM
200 lines
5.5 KiB
NASM
;*
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;* misc.nas
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;* Miscellaneous assembly functions
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;*
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;*---------------------------------------------------------------------------
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;* Copyright 1998-2006 Randy Heit
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without
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;* modification, are permitted provided that the following conditions
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;* are met:
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;*
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;* 1. Redistributions of source code must retain the above copyright
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;* notice, this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright
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;* notice, this list of conditions and the following disclaimer in the
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;* documentation and/or other materials provided with the distribution.
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;* 3. The name of the author may not be used to endorse or promote products
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;* derived from this software without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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;* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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;* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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;* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*---------------------------------------------------------------------------
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;*
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BITS 32
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%ifndef M_TARGET_LINUX
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%define DoBlending_MMX _DoBlending_MMX
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%define BestColor_MMX _BestColor_MMX
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%endif
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%ifdef M_TARGET_WATCOM
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SEGMENT DATA PUBLIC ALIGN=16 CLASS=DATA USE32
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SEGMENT DATA
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%else
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SECTION .data
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%endif
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Blending256:
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dd 0x01000100,0x00000100
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%ifdef M_TARGET_WATCOM
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SEGMENT CODE PUBLIC ALIGN=16 CLASS=CODE USE32
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SEGMENT CODE
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%else
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SECTION .text
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%endif
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;-----------------------------------------------------------
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;
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; DoBlending_MMX
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;
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; MMX version of DoBlending
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;
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; (DWORD *from, DWORD *to, count, tor, tog, tob, toa)
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;-----------------------------------------------------------
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GLOBAL DoBlending_MMX
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DoBlending_MMX:
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pxor mm0,mm0 ; mm0 = 0
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mov eax,[esp+4*4]
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shl eax,16
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mov edx,[esp+4*5]
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shl edx,8
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or eax,[esp+4*6]
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or eax,edx
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mov ecx,[esp+4*3] ; ecx = count
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movd mm1,eax ; mm1 = 00000000 00RRGGBB
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mov eax,[esp+4*7]
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shl eax,16
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mov edx,[esp+4*7]
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shl edx,8
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or eax,[esp+4*7]
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or eax,edx
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mov edx,[esp+4*2] ; edx = dest
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movd mm6,eax ; mm6 = 00000000 00AAAAAA
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punpcklbw mm1,mm0 ; mm1 = 000000RR 00GG00BB
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movq mm7,[Blending256]
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punpcklbw mm6,mm0 ; mm6 = 000000AA 00AA00AA
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mov eax,[esp+4*1] ; eax = source
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pmullw mm1,mm6 ; mm1 = 000000RR 00GG00BB (multiplied by alpha)
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psubusw mm7,mm6 ; mm7 = 000000aa 00aa00aa (one minus alpha)
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nop ; Does this actually pair on a Pentium?
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; Do four colors per iteration: Count must be a multiple of four.
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.loop movq mm2,[eax] ; mm2 = 00r2g2b2 00r1g1b1
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add eax,8
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movq mm3,mm2 ; mm3 = 00r2g2b2 00r1g1b1
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punpcklbw mm2,mm0 ; mm2 = 000000r1 00g100b1
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punpckhbw mm3,mm0 ; mm3 = 000000r2 00g200b2
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pmullw mm2,mm7 ; mm2 = 0000r1rr g1ggb1bb
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add edx,8
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pmullw mm3,mm7 ; mm3 = 0000r2rr g2ggb2bb
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sub ecx,2
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paddusw mm2,mm1
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psrlw mm2,8
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paddusw mm3,mm1
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psrlw mm3,8
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packuswb mm2,mm3 ; mm2 = 00r2g2b2 00r1g1b1
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movq [edx-8],mm2
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movq mm2,[eax] ; mm2 = 00r2g2b2 00r1g1b1
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add eax,8
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movq mm3,mm2 ; mm3 = 00r2g2b2 00r1g1b1
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punpcklbw mm2,mm0 ; mm2 = 000000r1 00g100b1
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punpckhbw mm3,mm0 ; mm3 = 000000r2 00g200b2
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pmullw mm2,mm7 ; mm2 = 0000r1rr g1ggb1bb
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add edx,8
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pmullw mm3,mm7 ; mm3 = 0000r2rr g2ggb2bb
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sub ecx,2
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paddusw mm2,mm1
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psrlw mm2,8
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paddusw mm3,mm1
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psrlw mm3,8
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packuswb mm2,mm3 ; mm2 = 00r2g2b2 00r1g1b1
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movq [edx-8],mm2
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jnz .loop
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emms
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ret
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;-----------------------------------------------------------
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;
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; BestColor_MMX
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;
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; Picks the closest matching color from a palette
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;
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; Passed FFRRGGBB and palette array in same format
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; FF is the index of the first palette entry to consider
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;
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;-----------------------------------------------------------
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GLOBAL BestColor_MMX
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GLOBAL @BestColor_MMX@8
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BestColor_MMX:
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mov ecx,[esp+4]
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mov edx,[esp+8]
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@BestColor_MMX@8:
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pxor mm0,mm0
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movd mm1,ecx ; mm1 = color searching for
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mov eax,257*257+257*257+257*257 ;eax = bestdist
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push ebx
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punpcklbw mm1,mm0
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mov ebx,ecx ; ebx = best color
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shr ecx,24 ; ecx = count
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and ebx,0xffffff
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push esi
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push ebp
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.loop movd mm2,[edx+ecx*4] ; mm2 = color considering now
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inc ecx
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punpcklbw mm2,mm0
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movq mm3,mm1
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psubsw mm3,mm2
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pmullw mm3,mm3 ; mm3 = color distance squared
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movd ebp,mm3 ; add the three components
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psrlq mm3,32 ; into ebp to get the real
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mov esi,ebp ; (squared) distance
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shr esi,16
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and ebp,0xffff
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add ebp,esi
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movd esi,mm3
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add ebp,esi
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jz .perf ; found a perfect match
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cmp eax,ebp
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jb .skip
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mov eax,ebp
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lea ebx,[ecx-1]
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.skip cmp ecx,256
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jne .loop
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mov eax,ebx
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pop ebp
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pop esi
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pop ebx
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emms
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ret
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.perf lea eax,[ecx-1]
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pop ebp
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pop esi
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pop ebx
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emms
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ret
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