mirror of
https://github.com/ZDoom/gzdoom-gles.git
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87d46ddd11
## 1.5.0 2020-09-28 * Drum note length expanding is now supported in real-time mode (Thanks to [Jean Pierre Cimalando](https://github.com/jpcima) for a work!) * Added support for OPNA chip with Neko Project II Kai YM2602 emulator usage (Thanks to [Jean Pierre Cimalando](https://github.com/jpcima) for a work!) * Added VGM file dumper which allows to output OPN2 commands into VGM file. (A new MIDI to VGM tool is now created with basing on libOPNMIDI) * Fixed an incorrect work of CC-121 (See https://github.com/Wohlstand/libADLMIDI/issues/227 for details) * Internality has been refactored and improved
628 lines
20 KiB
C++
628 lines
20 KiB
C++
// license:GPL-2.0+
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// copyright-holders:Jarek Burczynski
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/*
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**
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** File: ymdeltat.c
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**
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** YAMAHA DELTA-T adpcm sound emulation subroutine
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** used by fmopl.c (Y8950) and fm.c (YM2608 and YM2610/B)
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**
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** Base program is YM2610 emulator by Hiromitsu Shioya.
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** Written by Tatsuyuki Satoh
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** Improvements by Jarek Burczynski (bujar at mame dot net)
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**
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**
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** History:
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**
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** 03-08-2003 Jarek Burczynski:
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** - fixed BRDY flag implementation.
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**
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** 24-07-2003 Jarek Burczynski, Frits Hilderink:
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** - fixed delault value for control2 in YM_DELTAT_ADPCM_Reset
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**
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** 22-07-2003 Jarek Burczynski, Frits Hilderink:
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** - fixed external memory support
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**
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** 15-06-2003 Jarek Burczynski:
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** - implemented CPU -> AUDIO ADPCM synthesis (via writes to the ADPCM data reg $08)
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** - implemented support for the Limit address register
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** - supported two bits from the control register 2 ($01): RAM TYPE (x1 bit/x8 bit), ROM/RAM
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** - implemented external memory access (read/write) via the ADPCM data reg reads/writes
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** Thanks go to Frits Hilderink for the example code.
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**
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** 14-06-2003 Jarek Burczynski:
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** - various fixes to enable proper support for status register flags: BSRDY, PCM BSY, ZERO
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** - modified EOS handling
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**
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** 05-04-2003 Jarek Burczynski:
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** - implemented partial support for external/processor memory on sample replay
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**
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** 01-12-2002 Jarek Burczynski:
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** - fixed first missing sound in gigandes thanks to previous fix (interpolator) by ElSemi
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** - renamed/removed some YM_DELTAT struct fields
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**
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** 28-12-2001 Acho A. Tang
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** - added EOS status report on ADPCM playback.
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**
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** 05-08-2001 Jarek Burczynski:
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** - now_step is initialized with 0 at the start of play.
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**
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** 12-06-2001 Jarek Burczynski:
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** - corrected end of sample bug in YM_DELTAT_ADPCM_CALC.
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** Checked on real YM2610 chip - address register is 24 bits wide.
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** Thanks go to Stefan Jokisch (stefan.jokisch@gmx.de) for tracking down the problem.
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**
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** TO DO:
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** Check size of the address register on the other chips....
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**
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** Version 0.72
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**
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** sound chips that have this unit:
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** YM2608 OPNA
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** YM2610/B OPNB
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** Y8950 MSX AUDIO
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**
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*/
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#include "emu.h"
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#include "ymdeltat.h"
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#define YM_DELTAT_SHIFT (16)
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#define YM_DELTAT_DELTA_MAX (24576)
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#define YM_DELTAT_DELTA_MIN (127)
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#define YM_DELTAT_DELTA_DEF (127)
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#define YM_DELTAT_DECODE_RANGE 32768
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#define YM_DELTAT_DECODE_MIN (-(YM_DELTAT_DECODE_RANGE))
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#define YM_DELTAT_DECODE_MAX ((YM_DELTAT_DECODE_RANGE)-1)
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/* Forecast to next Forecast (rate = *8) */
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/* 1/8 , 3/8 , 5/8 , 7/8 , 9/8 , 11/8 , 13/8 , 15/8 */
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static CONSTEXPR int32_t ym_deltat_decode_tableB1[16] = {
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1, 3, 5, 7, 9, 11, 13, 15,
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-1, -3, -5, -7, -9, -11, -13, -15,
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};
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/* delta to next delta (rate= *64) */
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/* 0.9 , 0.9 , 0.9 , 0.9 , 1.2 , 1.6 , 2.0 , 2.4 */
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static CONSTEXPR int32_t ym_deltat_decode_tableB2[16] = {
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57, 57, 57, 57, 77, 102, 128, 153,
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57, 57, 57, 57, 77, 102, 128, 153
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};
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#if 0
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void YM_DELTAT::BRDY_callback()
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{
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logerror("BRDY_callback reached (flag set) !\n");
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/* set BRDY bit in status register */
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if(status_set_handler)
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if(status_change_BRDY_bit)
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(status_set_handler)(status_change_which_chip, status_change_BRDY_bit);
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}
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#endif
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uint8_t YM_DELTAT::ADPCM_Read()
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{
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uint8_t v = 0;
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/* external memory read */
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if ((portstate & 0xe0) == 0x20)
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{
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/* two dummy reads */
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if (memread)
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{
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now_addr = start << 1;
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memread--;
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return 0;
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}
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if (now_addr != (end << 1))
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{
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v = read_byte(device, now_addr>>1);
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/*logerror("YM Delta-T memory read $%08x, v=$%02x\n", now_addr >> 1, v);*/
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now_addr += 2; /* two nibbles at a time */
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/* reset BRDY bit in status register, which means we are reading the memory now */
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if (status_reset_handler && status_change_BRDY_bit)
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(status_reset_handler)(status_change_which_chip, status_change_BRDY_bit);
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/* setup a timer that will callback us in 10 master clock cycles for Y8950
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* in the callback set the BRDY flag to 1 , which means we have another data ready.
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* For now, we don't really do this; we simply reset and set the flag in zero time, so that the IRQ will work.
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*/
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/* set BRDY bit in status register */
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if (status_set_handler && status_change_BRDY_bit)
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(status_set_handler)(status_change_which_chip, status_change_BRDY_bit);
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}
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else
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{
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/* set EOS bit in status register */
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if (status_set_handler && status_change_EOS_bit)
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(status_set_handler)(status_change_which_chip, status_change_EOS_bit);
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}
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}
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return v;
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}
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/* 0-DRAM x1, 1-ROM, 2-DRAM x8, 3-ROM (3 is bad setting - not allowed by the manual) */
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static CONSTEXPR uint8_t dram_rightshift[4]={3,0,0,0};
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/* DELTA-T ADPCM write register */
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void YM_DELTAT::ADPCM_Write(int r, int v)
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{
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if (r >= 0x10) return;
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reg[r] = v; /* stock data */
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switch (r)
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{
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case 0x00:
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/*
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START:
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Accessing *external* memory is started when START bit (D7) is set to "1", so
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you must set all conditions needed for recording/playback before starting.
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If you access *CPU-managed* memory, recording/playback starts after
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read/write of ADPCM data register $08.
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REC:
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0 = ADPCM synthesis (playback)
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1 = ADPCM analysis (record)
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MEMDATA:
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0 = processor (*CPU-managed*) memory (means: using register $08)
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1 = external memory (using start/end/limit registers to access memory: RAM or ROM)
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SPOFF:
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controls output pin that should disable the speaker while ADPCM analysis
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RESET and REPEAT only work with external memory.
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some examples:
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value: START, REC, MEMDAT, REPEAT, SPOFF, x,x,RESET meaning:
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C8 1 1 0 0 1 0 0 0 Analysis (recording) from AUDIO to CPU (to reg $08), sample rate in PRESCALER register
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E8 1 1 1 0 1 0 0 0 Analysis (recording) from AUDIO to EXT.MEMORY, sample rate in PRESCALER register
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80 1 0 0 0 0 0 0 0 Synthesis (playing) from CPU (from reg $08) to AUDIO,sample rate in DELTA-N register
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a0 1 0 1 0 0 0 0 0 Synthesis (playing) from EXT.MEMORY to AUDIO, sample rate in DELTA-N register
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60 0 1 1 0 0 0 0 0 External memory write via ADPCM data register $08
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20 0 0 1 0 0 0 0 0 External memory read via ADPCM data register $08
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*/
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/* handle emulation mode */
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if (emulation_mode == EMULATION_MODE_YM2610)
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{
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v |= 0x20; /* YM2610 always uses external memory and doesn't even have memory flag bit. */
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v &= ~0x40; /* YM2610 has no rec bit */
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}
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portstate = v & (0x80|0x40|0x20|0x10|0x01); /* start, rec, memory mode, repeat flag copy, reset(bit0) */
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if (portstate & 0x80)/* START,REC,MEMDATA,REPEAT,SPOFF,--,--,RESET */
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{
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/* set PCM BUSY bit */
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PCM_BSY = 1;
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/* start ADPCM */
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now_step = 0;
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acc = 0;
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prev_acc = 0;
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adpcml = 0;
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adpcmd = YM_DELTAT_DELTA_DEF;
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now_data = 0;
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}
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if (portstate & 0x20) /* do we access external memory? */
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{
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now_addr = start << 1;
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memread = 2; /* two dummy reads needed before accesing external memory via register $08*/
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}
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else /* we access CPU memory (ADPCM data register $08) so we only reset now_addr here */
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{
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now_addr = 0;
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}
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if (portstate & 0x01)
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{
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portstate = 0x00;
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/* clear PCM BUSY bit (in status register) */
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PCM_BSY = 0;
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/* set BRDY flag */
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if (status_set_handler && status_change_BRDY_bit)
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(status_set_handler)(status_change_which_chip, status_change_BRDY_bit);
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}
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break;
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case 0x01: /* L,R,-,-,SAMPLE,DA/AD,RAMTYPE,ROM */
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/* handle emulation mode */
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if (emulation_mode == EMULATION_MODE_YM2610)
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{
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v |= 0x01; /* YM2610 always uses ROM as an external memory and doesn't tave ROM/RAM memory flag bit. */
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}
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pan = &output_pointer[(v >> 6) & 0x03];
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if ((control2 & 3) != (v & 3))
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{
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/*0-DRAM x1, 1-ROM, 2-DRAM x8, 3-ROM (3 is bad setting - not allowed by the manual) */
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if (DRAMportshift != dram_rightshift[v & 3])
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{
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DRAMportshift = dram_rightshift[v & 3];
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/* final shift value depends on chip type and memory type selected:
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8 for YM2610 (ROM only),
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5 for ROM for Y8950 and YM2608,
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5 for x8bit DRAMs for Y8950 and YM2608,
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2 for x1bit DRAMs for Y8950 and YM2608.
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*/
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/* refresh addresses */
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start = (reg[0x3] * 0x0100 | reg[0x2]) << (portshift - DRAMportshift);
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end = (reg[0x5] * 0x0100 | reg[0x4]) << (portshift - DRAMportshift);
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end += (1 << (portshift - DRAMportshift)) - 1;
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limit = (reg[0xd]*0x0100 | reg[0xc]) << (portshift - DRAMportshift);
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}
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}
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control2 = v;
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break;
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case 0x02: /* Start Address L */
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case 0x03: /* Start Address H */
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start = (reg[0x3] * 0x0100 | reg[0x2]) << (portshift - DRAMportshift);
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/*logerror("DELTAT start: 02=%2x 03=%2x addr=%8x\n",reg[0x2], reg[0x3],start );*/
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break;
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case 0x04: /* Stop Address L */
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case 0x05: /* Stop Address H */
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end = (reg[0x5]*0x0100 | reg[0x4]) << (portshift - DRAMportshift);
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end += (1 << (portshift - DRAMportshift)) - 1;
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/*logerror("DELTAT end : 04=%2x 05=%2x addr=%8x\n",reg[0x4], reg[0x5],end );*/
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break;
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case 0x06: /* Prescale L (ADPCM and Record frq) */
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case 0x07: /* Prescale H */
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break;
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case 0x08: /* ADPCM data */
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/*
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some examples:
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value: START, REC, MEMDAT, REPEAT, SPOFF, x,x,RESET meaning:
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C8 1 1 0 0 1 0 0 0 Analysis (recording) from AUDIO to CPU (to reg $08), sample rate in PRESCALER register
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E8 1 1 1 0 1 0 0 0 Analysis (recording) from AUDIO to EXT.MEMORY, sample rate in PRESCALER register
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80 1 0 0 0 0 0 0 0 Synthesis (playing) from CPU (from reg $08) to AUDIO,sample rate in DELTA-N register
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a0 1 0 1 0 0 0 0 0 Synthesis (playing) from EXT.MEMORY to AUDIO, sample rate in DELTA-N register
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60 0 1 1 0 0 0 0 0 External memory write via ADPCM data register $08
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20 0 0 1 0 0 0 0 0 External memory read via ADPCM data register $08
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*/
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/* external memory write */
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if ((portstate & 0xe0) == 0x60)
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{
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if (memread)
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{
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now_addr = start << 1;
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memread = 0;
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}
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/*logerror("YM Delta-T memory write $%08x, v=$%02x\n", now_addr >> 1, v);*/
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if (now_addr != (end << 1))
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{
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write_byte(device, now_addr >> 1, v);
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now_addr += 2; /* two nybbles at a time */
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/* reset BRDY bit in status register, which means we are processing the write */
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if (status_reset_handler && status_change_BRDY_bit)
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(status_reset_handler)(status_change_which_chip, status_change_BRDY_bit);
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/* setup a timer that will callback us in 10 master clock cycles for Y8950
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* in the callback set the BRDY flag to 1 , which means we have written the data.
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* For now, we don't really do this; we simply reset and set the flag in zero time, so that the IRQ will work.
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*/
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/* set BRDY bit in status register */
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if (status_set_handler && status_change_BRDY_bit)
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(status_set_handler)(status_change_which_chip, status_change_BRDY_bit);
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}
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else
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{
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/* set EOS bit in status register */
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if (status_set_handler && status_change_EOS_bit)
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(status_set_handler)(status_change_which_chip, status_change_EOS_bit);
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}
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return;
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}
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/* ADPCM synthesis from CPU */
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if ((portstate & 0xe0) == 0x80)
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{
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CPU_data = v;
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/* Reset BRDY bit in status register, which means we are full of data */
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if (status_reset_handler && status_change_BRDY_bit)
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(status_reset_handler)(status_change_which_chip, status_change_BRDY_bit);
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return;
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}
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break;
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case 0x09: /* DELTA-N L (ADPCM Playback Prescaler) */
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case 0x0a: /* DELTA-N H */
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delta = (reg[0xa] * 0x0100 | reg[0x9]);
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step = uint32_t(double(delta /* *(1<<(YM_DELTAT_SHIFT-16)) */) * freqbase);
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/*logerror("DELTAT deltan:09=%2x 0a=%2x\n",reg[0x9], reg[0xa]);*/
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break;
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case 0x0b: /* Output level control (volume, linear) */
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{
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const int32_t oldvol = volume;
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volume = (v & 0xff) * (output_range / 256) / YM_DELTAT_DECODE_RANGE;
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/* v * ((1<<16)>>8) >> 15;
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* thus: v * (1<<8) >> 15;
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* thus: output_range must be (1 << (15+8)) at least
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* v * ((1<<23)>>8) >> 15;
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* v * (1<<15) >> 15;
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*/
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/*logerror("DELTAT vol = %2x\n",v&0xff);*/
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if (oldvol != 0)
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{
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adpcml = int(double(adpcml) / double(oldvol) * double(volume));
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}
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}
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break;
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case 0x0c: /* Limit Address L */
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case 0x0d: /* Limit Address H */
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limit = (reg[0xd] * 0x0100 | reg[0xc]) << (portshift - DRAMportshift);
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/*logerror("DELTAT limit: 0c=%2x 0d=%2x addr=%8x\n",reg[0xc], reg[0xd],limit );*/
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break;
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}
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}
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void YM_DELTAT::ADPCM_Reset(int panidx, int mode, device_t *dev)
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{
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device = dev;
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now_addr = 0;
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now_step = 0;
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step = 0;
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start = 0;
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end = 0;
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limit = ~0; /* this way YM2610 and Y8950 (both of which don't have limit address reg) will still work */
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volume = 0;
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pan = &output_pointer[panidx];
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acc = 0;
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prev_acc = 0;
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adpcmd = 127;
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adpcml = 0;
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emulation_mode = uint8_t(mode);
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portstate = (emulation_mode == EMULATION_MODE_YM2610) ? 0x20 : 0;
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control2 = (emulation_mode == EMULATION_MODE_YM2610) ? 0x01 : 0; /* default setting depends on the emulation mode. MSX demo called "facdemo_4" doesn't setup control2 register at all and still works */
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DRAMportshift = dram_rightshift[control2 & 3];
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/* The flag mask register disables the BRDY after the reset, however
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** as soon as the mask is enabled the flag needs to be set. */
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/* set BRDY bit in status register */
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if (status_set_handler && status_change_BRDY_bit)
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(status_set_handler)(status_change_which_chip, status_change_BRDY_bit);
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}
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void YM_DELTAT::postload(uint8_t *regs)
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{
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/* to keep adpcml */
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volume = 0;
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/* update */
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for (int r = 1; r < 16; r++)
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ADPCM_Write(r, regs[r]);
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reg[0] = regs[0];
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/* current rom data */
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now_data = read_byte(device, now_addr >> 1);
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}
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void YM_DELTAT::savestate(device_t *device)
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{
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(void)device;
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#ifdef MAME_EMU_SAVE_H
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YM_DELTAT *const DELTAT = this; // makes the save name sensible
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device->save_item(NAME(DELTAT->portstate));
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device->save_item(NAME(DELTAT->now_addr));
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device->save_item(NAME(DELTAT->now_step));
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device->save_item(NAME(DELTAT->acc));
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device->save_item(NAME(DELTAT->prev_acc));
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device->save_item(NAME(DELTAT->adpcmd));
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device->save_item(NAME(DELTAT->adpcml));
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|
#endif
|
|
}
|
|
|
|
|
|
#define YM_DELTAT_Limit(val,max,min) \
|
|
{ \
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|
if ( val > max ) val = max; \
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|
else if ( val < min ) val = min; \
|
|
}
|
|
|
|
static inline void YM_DELTAT_synthesis_from_external_memory(YM_DELTAT *DELTAT)
|
|
{
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|
uint32_t step;
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|
int data;
|
|
|
|
DELTAT->now_step += DELTAT->step;
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|
if ( DELTAT->now_step >= (1<<YM_DELTAT_SHIFT) )
|
|
{
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|
step = DELTAT->now_step >> YM_DELTAT_SHIFT;
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|
DELTAT->now_step &= (1<<YM_DELTAT_SHIFT)-1;
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|
do{
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|
if ( DELTAT->now_addr == (DELTAT->limit<<1) )
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|
DELTAT->now_addr = 0;
|
|
|
|
if ( DELTAT->now_addr == (DELTAT->end<<1) ) { /* 12-06-2001 JB: corrected comparison. Was > instead of == */
|
|
if( DELTAT->portstate&0x10 ){
|
|
/* repeat start */
|
|
DELTAT->now_addr = DELTAT->start<<1;
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|
DELTAT->acc = 0;
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|
DELTAT->adpcmd = YM_DELTAT_DELTA_DEF;
|
|
DELTAT->prev_acc = 0;
|
|
}else{
|
|
/* set EOS bit in status register */
|
|
if(DELTAT->status_set_handler)
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|
if(DELTAT->status_change_EOS_bit)
|
|
(DELTAT->status_set_handler)(DELTAT->status_change_which_chip, DELTAT->status_change_EOS_bit);
|
|
|
|
/* clear PCM BUSY bit (reflected in status register) */
|
|
DELTAT->PCM_BSY = 0;
|
|
|
|
DELTAT->portstate = 0;
|
|
DELTAT->adpcml = 0;
|
|
DELTAT->prev_acc = 0;
|
|
return;
|
|
}
|
|
}
|
|
|
|
if( DELTAT->now_addr&1 ) data = DELTAT->now_data & 0x0f;
|
|
else
|
|
{
|
|
DELTAT->now_data = DELTAT->read_byte(DELTAT->device, DELTAT->now_addr>>1);
|
|
data = DELTAT->now_data >> 4;
|
|
}
|
|
|
|
DELTAT->now_addr++;
|
|
/* 12-06-2001 JB: */
|
|
/* YM2610 address register is 24 bits wide.*/
|
|
/* The "+1" is there because we use 1 bit more for nibble calculations.*/
|
|
/* WARNING: */
|
|
/* Side effect: we should take the size of the mapped ROM into account */
|
|
DELTAT->now_addr &= ( (1<<(24+1))-1);
|
|
|
|
/* store accumulator value */
|
|
DELTAT->prev_acc = DELTAT->acc;
|
|
|
|
/* Forecast to next Forecast */
|
|
DELTAT->acc += (ym_deltat_decode_tableB1[data] * DELTAT->adpcmd / 8);
|
|
YM_DELTAT_Limit(DELTAT->acc,YM_DELTAT_DECODE_MAX, YM_DELTAT_DECODE_MIN);
|
|
|
|
/* delta to next delta */
|
|
DELTAT->adpcmd = (DELTAT->adpcmd * ym_deltat_decode_tableB2[data] ) / 64;
|
|
YM_DELTAT_Limit(DELTAT->adpcmd,YM_DELTAT_DELTA_MAX, YM_DELTAT_DELTA_MIN );
|
|
|
|
/* ElSemi: Fix interpolator. */
|
|
/*DELTAT->prev_acc = prev_acc + ((DELTAT->acc - prev_acc) / 2 );*/
|
|
|
|
}while(--step);
|
|
|
|
}
|
|
|
|
/* ElSemi: Fix interpolator. */
|
|
DELTAT->adpcml = DELTAT->prev_acc * (int)((1<<YM_DELTAT_SHIFT)-DELTAT->now_step);
|
|
DELTAT->adpcml += (DELTAT->acc * (int)DELTAT->now_step);
|
|
DELTAT->adpcml = (DELTAT->adpcml>>YM_DELTAT_SHIFT) * (int)DELTAT->volume;
|
|
|
|
/* output for work of output channels (outd[OPNxxxx])*/
|
|
*(DELTAT->pan) += DELTAT->adpcml;
|
|
}
|
|
|
|
|
|
|
|
static inline void YM_DELTAT_synthesis_from_CPU_memory(YM_DELTAT *DELTAT)
|
|
{
|
|
uint32_t step;
|
|
int data;
|
|
|
|
DELTAT->now_step += DELTAT->step;
|
|
if ( DELTAT->now_step >= (1<<YM_DELTAT_SHIFT) )
|
|
{
|
|
step = DELTAT->now_step >> YM_DELTAT_SHIFT;
|
|
DELTAT->now_step &= (1<<YM_DELTAT_SHIFT)-1;
|
|
do{
|
|
if( DELTAT->now_addr&1 )
|
|
{
|
|
data = DELTAT->now_data & 0x0f;
|
|
|
|
DELTAT->now_data = DELTAT->CPU_data;
|
|
|
|
/* after we used CPU_data, we set BRDY bit in status register,
|
|
* which means we are ready to accept another byte of data */
|
|
if(DELTAT->status_set_handler)
|
|
if(DELTAT->status_change_BRDY_bit)
|
|
(DELTAT->status_set_handler)(DELTAT->status_change_which_chip, DELTAT->status_change_BRDY_bit);
|
|
}
|
|
else
|
|
{
|
|
data = DELTAT->now_data >> 4;
|
|
}
|
|
|
|
DELTAT->now_addr++;
|
|
|
|
/* store accumulator value */
|
|
DELTAT->prev_acc = DELTAT->acc;
|
|
|
|
/* Forecast to next Forecast */
|
|
DELTAT->acc += (ym_deltat_decode_tableB1[data] * DELTAT->adpcmd / 8);
|
|
YM_DELTAT_Limit(DELTAT->acc,YM_DELTAT_DECODE_MAX, YM_DELTAT_DECODE_MIN);
|
|
|
|
/* delta to next delta */
|
|
DELTAT->adpcmd = (DELTAT->adpcmd * ym_deltat_decode_tableB2[data] ) / 64;
|
|
YM_DELTAT_Limit(DELTAT->adpcmd,YM_DELTAT_DELTA_MAX, YM_DELTAT_DELTA_MIN );
|
|
|
|
|
|
}while(--step);
|
|
|
|
}
|
|
|
|
/* ElSemi: Fix interpolator. */
|
|
DELTAT->adpcml = DELTAT->prev_acc * (int)((1<<YM_DELTAT_SHIFT)-DELTAT->now_step);
|
|
DELTAT->adpcml += (DELTAT->acc * (int)DELTAT->now_step);
|
|
DELTAT->adpcml = (DELTAT->adpcml>>YM_DELTAT_SHIFT) * (int)DELTAT->volume;
|
|
|
|
/* output for work of output channels (outd[OPNxxxx])*/
|
|
*(DELTAT->pan) += DELTAT->adpcml;
|
|
}
|
|
|
|
|
|
|
|
/* ADPCM B (Delta-T control type) */
|
|
void YM_DELTAT::ADPCM_CALC()
|
|
{
|
|
/*
|
|
some examples:
|
|
value: START, REC, MEMDAT, REPEAT, SPOFF, x,x,RESET meaning:
|
|
80 1 0 0 0 0 0 0 0 Synthesis (playing) from CPU (from reg $08) to AUDIO,sample rate in DELTA-N register
|
|
a0 1 0 1 0 0 0 0 0 Synthesis (playing) from EXT.MEMORY to AUDIO, sample rate in DELTA-N register
|
|
C8 1 1 0 0 1 0 0 0 Analysis (recording) from AUDIO to CPU (to reg $08), sample rate in PRESCALER register
|
|
E8 1 1 1 0 1 0 0 0 Analysis (recording) from AUDIO to EXT.MEMORY, sample rate in PRESCALER register
|
|
|
|
60 0 1 1 0 0 0 0 0 External memory write via ADPCM data register $08
|
|
20 0 0 1 0 0 0 0 0 External memory read via ADPCM data register $08
|
|
|
|
*/
|
|
|
|
if ( (portstate & 0xe0)==0xa0 )
|
|
{
|
|
YM_DELTAT_synthesis_from_external_memory(this);
|
|
return;
|
|
}
|
|
|
|
if ( (portstate & 0xe0)==0x80 )
|
|
{
|
|
/* ADPCM synthesis from CPU-managed memory (from reg $08) */
|
|
YM_DELTAT_synthesis_from_CPU_memory(this); /* change output based on data in ADPCM data reg ($08) */
|
|
return;
|
|
}
|
|
|
|
//todo: ADPCM analysis
|
|
// if ( (portstate & 0xe0)==0xc0 )
|
|
// if ( (portstate & 0xe0)==0xe0 )
|
|
|
|
return;
|
|
}
|