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https://github.com/UberGames/ioef.git
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- align sse control word storage space to 16 byte boundary for snapvector
- replace some whitespace with tabs in snapvector.c - Give gcc a bit more freedom in choice of registers
This commit is contained in:
Thilo Schulz
parent
d9ea902c31
commit
664f8e578d
5 changed files with 52 additions and 39 deletions
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@ -28,7 +28,7 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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long qftolsse(float f)
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{
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register long retval;
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long retval;
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__asm__ volatile
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(
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@ -40,21 +40,25 @@ long qftolsse(float f)
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return retval;
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}
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void qvmftolsse(void)
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int qvmftolsse(void)
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{
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int retval;
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__asm__ volatile
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(
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"movss (" EDI ", " EBX ", 4), %%xmm0\n"
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"cvttss2si %%xmm0, " EAX "\n"
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:
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"cvttss2si %%xmm0, %0\n"
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: "=r" (retval)
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:
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: "%xmm0"
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);
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return retval;
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}
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long qftolx87(float f)
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{
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register long retval;
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long retval;
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__asm__ volatile
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(
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@ -68,13 +72,17 @@ long qftolx87(float f)
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return retval;
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}
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void qvmftolx87(void)
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int qvmftolx87(void)
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{
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int retval;
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__asm__ volatile
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(
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"flds (" EDI ", " EBX ", 4)\n"
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"fistpl (" EDI ", " EBX ", 4)\n"
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"mov (" EDI ", " EBX ", 4), " EAX "\n"
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:
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"mov (" EDI ", " EBX ", 4), %0\n"
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: "=r" (retval)
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);
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return retval;
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}
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@ -44,7 +44,7 @@ IFDEF idx64
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; qsnapvector using SSE
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qsnapvectorsse PROC
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sub rsp, 4
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sub rsp, 8
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stmxcsr [rsp] ; save SSE control word
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ldmxcsr ssecw ; set to round nearest
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@ -58,19 +58,19 @@ IFDEF idx64
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pop rdi
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ldmxcsr [rsp] ; restore sse control word to old value
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add rsp, 4
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add rsp, 8
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ret
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qsnapvectorsse ENDP
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ELSE
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qsnapvectorsse PROC
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sub esp, 4
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sub esp, 8
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stmxcsr [esp] ; save SSE control word
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ldmxcsr ssecw ; set to round nearest
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push edi
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mov edi, dword ptr 12[esp] ; maskmovdqu uses edi as implicit memory operand
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mov edi, dword ptr 16[esp] ; maskmovdqu uses edi as implicit memory operand
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movaps xmm1, ssemask ; initialize the mask register for maskmovdqu
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movups xmm0, [edi] ; here is stored our vector. Read 4 values in one go
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cvtps2dq xmm0, xmm0 ; convert 4 single fp to int
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@ -79,7 +79,7 @@ ELSE
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pop edi
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ldmxcsr [esp] ; restore sse control word to old value
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add esp, 4
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add esp, 8
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ret
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qsnapvectorsse ENDP
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@ -25,6 +25,7 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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/*
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* GNU inline asm version of qsnapvector
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* See MASM snapvector.asm for commentary
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*/
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static unsigned char ssemask[16] __attribute__((aligned(16))) =
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@ -32,29 +33,33 @@ static unsigned char ssemask[16] __attribute__((aligned(16))) =
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"\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\x00\x00\x00\x00"
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};
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static unsigned int ssecw __attribute__((aligned(16))) = 0x00001F80;
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static unsigned short fpucw = 0x037F;
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static const unsigned int ssecw __attribute__((aligned(16))) = 0x00001F80;
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static const unsigned short fpucw = 0x037F;
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void qsnapvectorsse(vec3_t vec)
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{
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uint32_t oldcw __attribute__((aligned(16)));
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__asm__ volatile
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(
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"sub $4, " ESP "\n"
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"stmxcsr (" ESP ")\n"
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"stmxcsr %3\n"
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"ldmxcsr %1\n"
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"movaps (%0), %%xmm1\n"
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"movups (" EDI "), %%xmm0\n"
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"movups (%2), %%xmm0\n"
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"cvtps2dq %%xmm0, %%xmm0\n"
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"cvtdq2ps %%xmm0, %%xmm0\n"
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// vec MUST reside in register rdi as maskmovdqu uses
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// it as an implicit operand. The "D" constraint makes
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// sure of that.
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"maskmovdqu %%xmm1, %%xmm0\n"
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"ldmxcsr (" ESP ")\n"
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"add $4, " ESP "\n"
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"ldmxcsr %3\n"
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:
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: "r" (ssemask), "m" (ssecw), "D" (vec)
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: "r" (ssemask), "m" (ssecw), "D" (vec), "m" (oldcw)
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: "memory", "%xmm0", "%xmm1"
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);
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}
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#define QROUNDX87(src) \
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@ -67,16 +72,16 @@ void qsnapvectorx87(vec3_t vec)
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{
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__asm__ volatile
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(
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"sub $2, " ESP "\n"
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"fnstcw (" ESP ")\n"
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"fldcw %0\n"
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QROUNDX87("(%1)")
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QROUNDX87("4(%1)")
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QROUNDX87("8(%1)")
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"fldcw (" ESP ")\n"
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"add $2, " ESP "\n"
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:
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: "m" (fpucw), "r" (vec)
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: "memory"
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"sub $2, " ESP "\n"
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"fnstcw (" ESP ")\n"
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"fldcw %0\n"
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QROUNDX87("(%1)")
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QROUNDX87("4(%1)")
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QROUNDX87("8(%1)")
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"fldcw (" ESP ")\n"
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"add $2, " ESP "\n"
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:
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: "m" (fpucw), "r" (vec)
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: "memory"
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);
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}
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@ -91,10 +91,10 @@ cvar_t *com_homepath;
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cvar_t *com_busyWait;
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#if idx64
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void (*Q_VMftol)(void);
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int (*Q_VMftol)(void);
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#elif id386
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long (QDECL *Q_ftol)(float f);
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void (QDECL *Q_VMftol)(void);
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int (QDECL *Q_VMftol)(void);
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void (QDECL *Q_SnapVector)(vec3_t vec);
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#endif
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@ -423,23 +423,23 @@ int Q_isnan(float x);
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#if idx64
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extern long qftolsse(float f);
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extern void qvmftolsse(void);
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extern int qvmftolsse(void);
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extern void qsnapvectorsse(vec3_t vec);
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#define Q_ftol qftolsse
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#define Q_SnapVector qsnapvectorsse
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extern void (*Q_VMftol)(void);
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extern int (*Q_VMftol)(void);
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#elif id386
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extern long QDECL qftolx87(float f);
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extern long QDECL qftolsse(float f);
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extern void QDECL qvmftolx87(void);
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extern void QDECL qvmftolsse(void);
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extern int QDECL qvmftolx87(void);
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extern int QDECL qvmftolsse(void);
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extern void QDECL qsnapvectorx87(vec3_t vec);
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extern void QDECL qsnapvectorsse(vec3_t vec);
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extern long (QDECL *Q_ftol)(float f);
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extern void (QDECL *Q_VMftol)(void);
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extern int (QDECL *Q_VMftol)(void);
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extern void (QDECL *Q_SnapVector)(vec3_t vec);
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#else
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#define Q_ftol(f) lrintf((f))
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