mirror of
https://github.com/ReactionQuake3/reaction.git
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assembly code got messed up
This commit is contained in:
Bryce Hutchings
parent
6dc007dea1
commit
1caa63369f
1 changed files with 144 additions and 101 deletions
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@ -5,6 +5,9 @@
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// $Log$
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// $Log$
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// Revision 1.9 2002/06/16 20:51:10 niceass
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// assembly code got messed up
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//
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// Revision 1.8 2002/06/16 20:06:14 jbravo
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// Revision 1.8 2002/06/16 20:06:14 jbravo
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// Reindented all the source files with "indent -kr -ut -i8 -l120 -lc120 -sob -bad -bap"
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// Reindented all the source files with "indent -kr -ut -i8 -l120 -lc120 -sob -bad -bap"
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//
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//
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@ -987,7 +990,7 @@ int BoxOnPlaneSide(vec3_t emins, vec3_t emaxs, struct cplane_s *p)
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#pragma warning( disable: 4035 )
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#pragma warning( disable: 4035 )
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__declspec(naked)
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__declspec(naked)
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int BoxOnPlaneSide(vec3_t emins, vec3_t emaxs, struct cplane_s *p)
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int BoxOnPlaneSide (vec3_t emins, vec3_t emaxs, struct cplane_s *p)
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{
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{
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static int bops_initialized;
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static int bops_initialized;
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static int Ljmptab[8];
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static int Ljmptab[8];
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@ -995,187 +998,227 @@ int BoxOnPlaneSide(vec3_t emins, vec3_t emaxs, struct cplane_s *p)
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__asm {
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__asm {
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push ebx
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push ebx
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cmp bops_initialized, 1
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je initialized
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cmp bops_initialized, 1
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mov bops_initialized, 1
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je initialized
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mov Ljmptab[0 * 4], offset Lcase0
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mov bops_initialized, 1
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mov Ljmptab[1 * 4], offset Lcase1
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mov Ljmptab[2 * 4], offset Lcase2
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mov Ljmptab[0*4], offset Lcase0
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mov Ljmptab[3 * 4], offset Lcase3
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mov Ljmptab[1*4], offset Lcase1
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mov Ljmptab[4 * 4], offset Lcase4
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mov Ljmptab[2*4], offset Lcase2
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mov Ljmptab[5 * 4], offset Lcase5
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mov Ljmptab[3*4], offset Lcase3
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mov Ljmptab[6 * 4], offset Lcase6
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mov Ljmptab[4*4], offset Lcase4
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mov Ljmptab[7 * 4], offset Lcase7 initialized:mov edx, dword ptr[4 + 12 + esp]
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mov Ljmptab[5*4], offset Lcase5
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mov ecx, dword ptr[4 + 4 + esp]
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mov Ljmptab[6*4], offset Lcase6
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xor eax, eax mov ebx, dword ptr[4 + 8 + esp]
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mov Ljmptab[7*4], offset Lcase7
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mov al, byte ptr[17 + edx]
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cmp al, 8 jge Lerror fld dword ptr[0 + edx]
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initialized:
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mov edx,dword ptr[4+12+esp]
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mov ecx,dword ptr[4+4+esp]
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xor eax,eax
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mov ebx,dword ptr[4+8+esp]
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mov al,byte ptr[17+edx]
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cmp al,8
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jge Lerror
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fld dword ptr[0+edx]
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fld st(0)
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fld st(0)
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jmp dword ptr[Ljmptab + eax * 4] Lcase0:fmul dword ptr[ebx]
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jmp dword ptr[Ljmptab+eax*4]
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fld dword ptr[0 + 4 + edx]
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Lcase0:
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fmul dword ptr[ebx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ecx]
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fmul dword ptr[ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase1:fmul dword ptr[ecx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase1:
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fmul dword ptr[ecx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ebx]
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fmul dword ptr[ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase2:fmul dword ptr[ebx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase2:
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fmul dword ptr[ebx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ecx]
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fmul dword ptr[ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase3:fmul dword ptr[ecx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase3:
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fmul dword ptr[ecx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ebx]
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fmul dword ptr[ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase4:fmul dword ptr[ebx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase4:
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fmul dword ptr[ebx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ecx]
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fmul dword ptr[ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase5:fmul dword ptr[ecx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase5:
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fmul dword ptr[ecx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ebx]
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fmul dword ptr[ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase6:fmul dword ptr[ebx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase6:
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fmul dword ptr[ebx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ecx]
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fmul dword ptr[ecx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0)
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faddp st(2),st(0)
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jmp LSetSides Lcase7:fmul dword ptr[ecx]
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jmp LSetSides
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fld dword ptr[0 + 4 + edx]
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Lcase7:
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fmul dword ptr[ecx]
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fld dword ptr[0+4+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[ebx]
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fmul dword ptr[ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[4 + ecx]
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fmul dword ptr[4+ecx]
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fld dword ptr[0 + 8 + edx]
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fld dword ptr[0+8+edx]
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fxch st(2)
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fxch st(2)
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fmul dword ptr[4 + ebx]
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fmul dword ptr[4+ebx]
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fxch st(2)
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fxch st(2)
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fld st(0)
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fld st(0)
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fmul dword ptr[8 + ecx]
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fmul dword ptr[8+ecx]
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fxch st(5)
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fxch st(5)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fmul dword ptr[8 + ebx]
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fmul dword ptr[8+ebx]
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fxch st(1)
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fxch st(1)
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faddp st(3), st(0)
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faddp st(3),st(0)
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fxch st(3)
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fxch st(3)
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faddp st(2), st(0) LSetSides:faddp st(2), st(0)
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faddp st(2),st(0)
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fcomp dword ptr[12 + edx]
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LSetSides:
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xor ecx, ecx fnstsw ax fcomp dword ptr[12 + edx]
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faddp st(2),st(0)
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and ah, 1
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fcomp dword ptr[12+edx]
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xor ah, 1
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xor ecx,ecx
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add cl, ah fnstsw ax and ah, 1 add ah, ah add cl, ah pop ebx mov eax, ecx ret Lerror:int 3}}
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fnstsw ax
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fcomp dword ptr[12+edx]
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and ah,1
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xor ah,1
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add cl,ah
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fnstsw ax
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and ah,1
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add ah,ah
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add cl,ah
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pop ebx
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mov eax,ecx
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ret
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Lerror:
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int 3
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}
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}
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#pragma warning( default: 4035 )
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#pragma warning( default: 4035 )
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#endif
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#endif
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#endif
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#endif
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