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Intel hardware requires 32-byte alignment for lvec4 and dvec4. Unfortunately, it turns out that my attempts to align progs data in qfcc went awry do to the order block sizes are calculated when writing the progs. |
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.. | ||
test | ||
convert.py | ||
hops.py | ||
Makemodule.am | ||
opcodes.py | ||
pr_builtins.c | ||
pr_debug.c | ||
pr_edict.c | ||
pr_exec.c | ||
pr_load.c | ||
pr_opcode.c | ||
pr_parse.c | ||
pr_resolve.c | ||
pr_resource.c | ||
pr_strings.c | ||
pr_v6p_opcode.c | ||
pr_zone.c | ||
swizzle.py |